WIP vdiv regulator control
authorDan White <dan@whiteaudio.com>
Mon, 30 Jan 2012 18:18:54 +0000 (12:18 -0600)
committerDan White <dan@whiteaudio.com>
Mon, 30 Jan 2012 18:18:54 +0000 (12:18 -0600)
commitd773957e2790a0dfa8fc2f30ddd93d06150d221b
tree0171f9570d7ef405ea915c29f7b735e9f03b120d
parentf59a40febe510341274612ece173bdf5b6851741
WIP vdiv regulator control
sch-pcb/devboard/vreg.py