doc update

diff --git a/vwf2pwl.py b/vwf2pwl.py
index c90ec80744cda0f5eddcd9649937ad86813ab305..306a4bfb662118ae4b502782b653f9acf573501a 100755 (executable)
--- a/vwf2pwl.py
+++ b/vwf2pwl.py
@@ -47,7 +47,7 @@ clock as "Vclock clock 0 PWL ..." with a rising edge at every bittime with an
 offset of clockdelay.  Hence, set "clockdelay=" to the maximum setup time of
 your registers and the data on each line will be clocked in at the right time.
 Parameter "clockrisefall=" is optional to separately specify the clock rise/
-fall time.
+fall time if it is different from the data lines rise/fall.
 '''
 
 
@@ -64,6 +64,10 @@ def warn(s):
     print 'WARNING:', s
 
 
+def output(s):
+    fpwl.write(s + '\n')
+
+
 def mkvwf(d):
     t = Decimal('0.0')
 
@@ -77,6 +81,7 @@ def mkvwf(d):
     tb = bittime - risefall
     t += trf + tb
     for bit in d[1:]:
+        # only output a point when there is a change
         if bit != lastbit:
             ti = t + trf
             tf = ti + tb
@@ -85,7 +90,7 @@ def mkvwf(d):
             output('+ %s %s' % (str(t), str(lastbitv)))
             output('+ %s %s' % (str(ti), str(bitv)))
             #output('+ %s %s' % (str(tf), str(bitv)))
-        
+
         t += trf + tb
         lastbit = bit
 
@@ -117,6 +122,8 @@ def unit(s):
 
 
 
+
+
 if len(sys.argv) < 2:
     usage()
     sys.exit(1)
@@ -178,8 +185,7 @@ for line in fvwf:
         data[inputs[i]].append(bit)
         i += 1
 
-#outputs
-output = lambda s: fpwl.write(s + '\n')
+
 
 #get the numbers
 risefall = unit(params['risefall'])
@@ -210,7 +216,7 @@ if params['clockdelay']:
 #output each input source
 for name in inputs:
     d = data[name]
-    
+
     s = 'V%s %s 0 PWL' % (name, name)
     info(s)
     output(s)