--- /dev/null
+/*---------------------------------------------------------------------------*\
+
+ FILE........: leds_switches.h
+ AUTHOR......: David Rowe
+ DATE CREATED: 18 July 2014
+
+ Functions for controlling LEDs and reading switches on SM1000.
+
+\*---------------------------------------------------------------------------*/
+
+/*
+ Copyright (C) 2014 David Rowe
+
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License version 2.1, as
+ published by the Free Software Foundation. This program is
+ distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __LEDS_SWITCHES__
+#define __LEDS_SWITCHES__
+
+void leds_switches_init(void);
+void led_pwr(int state);
+void led_ptt(int state);
+void led_rt(int state);
+void led_err(int state);
+
+#endif
#define SINE_SAMPLES 32\r
\r
\r
-/* 32 sample sine wave which at Fs=16kHz will be 500Hz. Not sampels\r
+/* 32 sample sine wave which at Fs=16kHz will be 500Hz. Note samples\r
are 16 bit 2's complement, the DAC driver convertsto 12 bit\r
unsigned. */\r
\r
short aSine[] = {\r
- -16, 6384, 12528, 18192, 23200, 27232, 30256, 32128, 32752, 32128,\r
- 30256, 27232, 23152, 18192, 12528, 6384, -16, -6416, -12560, -18224,\r
- -23184, -27264, -30288, -32160, -32768, -32160, -30288, -27264, -23184, -18224,\r
- -12560, -6416\r
+ -16, 6384, 12528, 18192, 23200, 27232, 30256, 32128,\r
+ 32752, 32128, 30256, 27232, 23152, 18192, 12528, 6384,\r
+ -16, -6416, -12560, -18224, -23184, -27264, -30288, -32160,\r
+ -32768, -32160, -30288, -27264, -23184, -18224, -12560, -6416\r
};\r
\r
int main(void) {\r
\r
while (1) {\r
\r
- /* keep DAC FIFO topped up */\r
+ /* keep DAC FIFOs topped up */\r
\r
+ dac1_write((short*)aSine, SINE_SAMPLES);\r
dac2_write((short*)aSine, SINE_SAMPLES);\r
}\r
\r
AUTHOR......: David Rowe\r
DATE CREATED: 18 July 2014\r
\r
- Profiling Codec 2 operation on the STM32F4.\r
+ Profiling FDMDV modem operation on the STM32F4.\r
\r
\*---------------------------------------------------------------------------*/\r
\r
int *tx_bits;\r
int *rx_bits;\r
COMP tx_fdm[2*FDMDV_NOM_SAMPLES_PER_FRAME];\r
- int i, nin, reliable_sync_bit, sync_bit;\r
+ int i, nin, reliable_sync_bit, sync_bit, bit_errors, ntest_bits, test_frame_sync;\r
+ short *error_pattern;\r
struct FDMDV_STATS stats;\r
TIMER_VAR(mod_start, demod_start);\r
\r
+ machdep_timer_init ();\r
fdmdv = fdmdv_create(FDMDV_NC);\r
\r
bits_per_fdmdv_frame = fdmdv_bits_per_frame(fdmdv);\r
bits_per_codec_frame = 2*fdmdv_bits_per_frame(fdmdv);\r
tx_bits = (int*)malloc(sizeof(int)*bits_per_codec_frame); assert(tx_bits != NULL);\r
rx_bits = (int*)malloc(sizeof(int)*bits_per_codec_frame); assert(rx_bits != NULL);\r
+ error_pattern = (short*)malloc(fdmdv_error_pattern_size(fdmdv)*sizeof(int)); assert(error_pattern != NULL);\r
\r
nin = FDMDV_NOM_SAMPLES_PER_FRAME;\r
\r
fdmdv_mod(fdmdv, &tx_fdm[FDMDV_NOM_SAMPLES_PER_FRAME], &tx_bits[bits_per_fdmdv_frame], &sync_bit);\r
assert(sync_bit == 0);\r
\r
- TIMER_SAMPLE_AND_LOG(demod_start, mod_start, " enc"); \r
+ TIMER_SAMPLE_AND_LOG(demod_start, mod_start, " mod"); \r
\r
fdmdv_demod(fdmdv, rx_bits, &reliable_sync_bit, tx_fdm, &nin);\r
- fdmdv_demod(fdmdv, rx_bits, &reliable_sync_bit, &tx_fdm[FDMDV_NOM_SAMPLES_PER_FRAME], &nin);\r
- TIMER_SAMPLE_AND_LOG2(demod_start, " dec"); \r
- TIMER_SAMPLE_AND_LOG2(mod_start, " enc & dec"); \r
+ fdmdv_demod(fdmdv, &rx_bits[bits_per_fdmdv_frame], &reliable_sync_bit, &tx_fdm[FDMDV_NOM_SAMPLES_PER_FRAME], &nin);\r
+ TIMER_SAMPLE_AND_LOG2(demod_start, " demod"); \r
+ TIMER_SAMPLE_AND_LOG2(mod_start, " mod & demod"); \r
\r
fdmdv_get_demod_stats(fdmdv, &stats);\r
- printf("frame: %d sync: %d reliable_sync_bit: %d SNR: %3.2f\n", i, stats.sync, reliable_sync_bit, (double)stats.snr_est);\r
+ fdmdv_put_test_bits(fdmdv, &test_frame_sync, error_pattern, &bit_errors, &ntest_bits, rx_bits);\r
+\r
+ printf("frame: %d sync: %d reliable_sync_bit: %d SNR: %3.2f test_frame_sync: %d\n", \r
+ i, stats.sync, reliable_sync_bit, (double)stats.snr_est, test_frame_sync);\r
machdep_timer_print_logged_samples();\r
}\r
\r
--- /dev/null
+/*---------------------------------------------------------------------------*\
+
+ FILE........: leds_switches.c
+ AUTHOR......: David Rowe
+ DATE CREATED: 18 July 2014
+
+ Functions for controlling LEDs and reading switches on SM1000.
+
+\*---------------------------------------------------------------------------*/
+
+/*
+ Copyright (C) 2014 David Rowe
+
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License version 2.1, as
+ published by the Free Software Foundation. This program is
+ distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>.
+*/
+
+#define LED_PWR 12
+#define LED_PTT 13
+#define LED_RT 14
+#define LED_ERR 15
+
+#include "stm32f4xx_conf.h"
+#include "stm32f4xx.h"
+#include "leds_switches.h"
+
+void leds_switches_init(void) {
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN; // enable the clock to GPIOD
+
+ // Set pins as general purpose IOs
+
+ GPIOD->MODER = (2 << LED_PWR) | (2 << LED_PTT) | (2 << LED_RT) | (2 << LED_ERR);
+}
+
+void led_pwr(int state) {
+ if (state)
+ GPIOD->ODR = (1 << LED_PWR);
+ else
+ GPIOD->ODR &= ~(1 << LED_PWR);
+}
+
+void led_ptt(int state) {
+ if (state)
+ GPIOD->ODR = (1 << LED_PTT);
+ else
+ GPIOD->ODR &= ~(1 << LED_PTT);
+}
+
+void led_rt(int state) {
+ if (state)
+ GPIOD->ODR = (1 << LED_RT);
+ else
+ GPIOD->ODR &= ~(1 << LED_RT);
+}
+
+void led_err(int state) {
+ if (state)
+ GPIOD->ODR = (1 << LED_ERR);
+ else
+ GPIOD->ODR &= ~(1 << LED_ERR);
+}
+
#include "codec2_fifo.h"\r
#include "stm32f4_dac.h"\r
\r
-#define DAC_DHR12R2_ADDRESS 0x40007414\r
+/* write to these registers for 12 bit left aligned data, as per data sheet \r
+ make sure 4 least sig bits set to 0 */\r
+\r
+#define DAC_DHR12L1_ADDRESS 0x4000740c\r
#define DAC_DHR12L2_ADDRESS 0x40007418\r
\r
#define DAC_BUF_SZ 320\r
\r
DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;\r
DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;\r
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;\r
+ DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
DAC_Init(DAC_Channel_1, &DAC_InitStructure);\r
\r
/* DMA1_Stream5 channel7 configuration **************************************/\r
\r
DMA_DeInit(DMA1_Stream5);\r
DMA_InitStructure.DMA_Channel = DMA_Channel_7; \r
- DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12R2_ADDRESS;\r
+ DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12L1_ADDRESS;\r
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dac1_buf;\r
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;\r
DMA_InitStructure.DMA_BufferSize = DAC_BUF_SZ;\r
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;\r
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;\r
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;\r
- DMA_Init(DMA1_Stream6, &DMA_InitStructure);\r
+ DMA_Init(DMA1_Stream5, &DMA_InitStructure);\r
\r
/* Enable DMA Half & Complete interrupts */\r
\r
\r
DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;\r
DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;\r
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;\r
+ DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
DAC_Init(DAC_Channel_2, &DAC_InitStructure);\r
\r
/* DMA1_Stream6 channel7 configuration **************************************/\r
\r
for(i=0; i<DAC_BUF_SZ/2; i++) {\r
sam = (int)signed_buf[i] + 32768;\r
- dac1_buf[i] = (unsigned short)(sam);\r
+ dac1_buf[i] = (unsigned short)(sam & 0xfff000);\r
}\r
\r
/* Clear DMA Stream Transfer Complete interrupt pending bit */\r
\r
for(i=0; i<DAC_BUF_SZ/2; i++) {\r
sam = (int)signed_buf[i] + 32768;\r
- dac1_buf[i+DAC_BUF_SZ/2] = (unsigned short)(sam);\r
+ dac1_buf[i+DAC_BUF_SZ/2] = (unsigned short)(sam & 0xfff000);\r
}\r
\r
/* Clear DMA Stream Transfer Complete interrupt pending bit */\r
\r
for(i=0; i<DAC_BUF_SZ/2; i++) {\r
sam = (int)signed_buf[i] + 32768;\r
- dac2_buf[i] = (unsigned short)(sam);\r
+ dac2_buf[i] = (unsigned short)(sam & 0xfff000);\r
}\r
\r
/* Clear DMA Stream Transfer Complete interrupt pending bit */\r
dac_underflow++;\r
}\r
\r
- /* convert to unsigned */\r
+ /* convert to unsigned */\r
\r
for(i=0; i<DAC_BUF_SZ/2; i++) {\r
sam = (int)signed_buf[i] + 32768;\r
- dac2_buf[i+DAC_BUF_SZ/2] = (unsigned short)(sam);\r
+ dac2_buf[i+DAC_BUF_SZ/2] = (unsigned short)(sam & 0xfff000);\r
}\r
\r
/* Clear DMA Stream Transfer Complete interrupt pending bit */\r