--- /dev/null
+
+[_] 0% Analog pins
+ [_] 0% Single OTA
+ [_] ota_slow - 2v4 logic
+ [_] ota_slowinv - 2v4 logic
+ [_] ota_biasa - current sink
+ [_] ota_biasb - current sink
+ [_] ota_biasccp - voltage bias
+ [_] ota_biasccn - voltage bias
+ [_] ota_ina - signal input
+ [_] ota_inb - signal input
+ [_] ota_cmi - signal input
+ [_] ota_out - signal output
+ [_] 0% AtoI Main Channels
+ [_] 0% Integrator Bias
+ [_] biasp - main current setting voltage
+ : read only unless...
+ [_] send to ADC
+ [_] biasccp - cascode bias voltage
+ : read only unless...
+ [_] send to ADC
+ [_] biasR - resistance in bias loop generator
+ : TODO expected R range
+ : 2 resistors, bottom fixed and known C-V converter for ADC
+ [_] send to ADC
+ [_] 0% Mux Buffer Bias
+ [_] buf_biasp - main current setting voltage
+ : read only unless...
+ [_] send to ADC
+ [_] buf_biasccp - cascode bias voltage
+ : read only unless...
+ [_] send to ADC
+ [_] buf_biasR - resistance in bias loop generator
+ : TODO expected R range
+ : 2 resistors, bottom fixed and known C-V converter for ADC
+ [_] send to ADC
+ [_] 0% Signal Inputs
+ [_] INA - diff signal
+ [_] from DAC
+ [_] INB - diff signal
+ [_] from DAC
+ [_] CMI - AREF analog "0"
+ [_] from AREF generator
+ [_] 0% Signal Outputs
+ : full AVDD-AVSS range
+ [_] mux0_outA - AtoI integrator mux/buffer output
+ [_] send to ADC
+ [_] mux0_outB - AtoI integrator mux/buffer output
+ [_] send to ADC
+ [_] arb_out0 - Arb output(0) direct
+ [_] send to ADC
+ [_] arb_out1 - Arb output(1) direct
+ [_] send to ADC
+ [_] mux1_outA - Arb mux/buffer output
+ [_] send to ADC
+ [_] mux1_outB - Arb mux/buffer output
+ [_] send to ADC
+
+[_] % Digital Pins
+
+Notes
+ USCI_A0 on cc430 supports SPI, UART
+ USCI_B0 on cc430 supports SPI, I2C
+ After boot, r9 holds RAMER count
+
+Connections
+ [_] 0% ns430
+ : SPI0 - flash
+ : SPI1 - AtoI digital
+ : UART0 - bootloader, comms
+ : UART1 - ???
+ : I2C - DigiPots (biasR, LDO)
+ [_] % Digital Pins
+ [_] 94 - GPOut33 / CS1_mux (pad mux)
+ [_] 95 - GPOut32 / CS1_conf (pad mux)
+ [_] 96 - GPOut1 / MULT1 (pad mux)
+ [_] 97 - GPOut0 / MULT0 (pad mux)
+ [_] 98 - PB7 / RESET (pad mux)
+ [_] 99 - PB8 / NCO_CLK / timer0 (pad mux)
+ [_] 100 - INT_SPI
+ : low: inputs from off-chip to internal digital signals
+ : high - pads are outputs, monitor internal digital signals
+ [_] 1 - DOUT0_mux
+ : jumper to MISO1
+ [_] 2 - DOUT0_conf
+ : jumper to MISO1
+ [_] 3 - PA15 / CS0_conf (pad mux)
+ [_] 4 - PA14 / RXD1
+ [_] 5 - PA13 / TXD1
+ [_] 6 - PA12 / SCLK1 (pad mux)
+ : internal AtoI SPI connection
+ [_] 7 - PA11 / MOSI1 (pad mux)
+ : internal AtoI SPI connection
+ [_] 8 - PA10 / MISO1
+ : opt jumpers from DOUT_x
+ [_] 9 - PA9 / SCL / endianness
+ : low - noswap
+ : high - swap bytes
+ : connect to DigiPots
+ [_] 10- PA8 / SDA
+ : connect to DigiPots
+ [_] 11- PA7 / BSL / CS0_mux (pad mux)
+ : low - run BSL
+ : high - copy/run from flash
+ [_] 12- PA6 / IRQ
+ [_] 13- PA5 / RDX0
+ : bootloader
+ [_] 14- PA4 / TXD0
+ : bootloader
+ [_] 15- PA3 / SCLK0
+ : to flash
+ [_] 16- PA2 / MOSI0
+ : to flash
+ [_] 17- PA1 / MISO0
+ : to flash
+ [_] 18- PA0 / CS_flash
+ : to flash
+ [_] 0% ADC0 - shared SPI bus
+ : ADS8201 (sampled from TI)
+ : QFN-24
+ : 8ch 12bit 2.2/2.7 Vmin
+ [_] 0% Control
+ [_] SPI1 on ns430
+ [_] USCI_A0 or USCI_B0 on cc430
+ [_] 0% Input Signals
+ [_] 0 - mux0_outA
+ [_] 1 - mux0_outB
+ [_] 2 - mux1_outA
+ : or by pcb switch arb_out0 - hardwired to arb0
+ [_] 3 - mux1_outB
+ : or by pcb switch arb_out1 - hardwired to arb0
+ [_] 4 - biasR - to infer bias current
+ : diff with 5 for Vrdac0, or SE for PTAT n*Vt*ln(k)
+ : buffered by max9912
+ [_] 5 - 1k biasR Vx
+ : buffered by max9912
+ [_] 6 - buf_biasR - to infer bias current
+ : diff with 7 for Vrdac1, or SE for PTAT n*Vt*ln(k)
+ : buffered by max9912
+ [_] 7 - 1k buf_biasR Vx
+ : buffered by max9912
+ [_] 0% Pins
+ [_] IN[7:0]
+ [_] /RST - hardware reset
+ [_] BUSY/INT - indication of activity
+ [_] SCLK, SDI, SDO, /CS
+ [_] DGND - interface gnd
+ [_] /CONVST
+ [_] VD - interface supply
+ [_] VA - analog supply
+ [_] REF - external reference
+ [_] REFGND - reference gnd
+ [_] AGND - analog gnd
+ [_] ADCIN - ADC input
+ [_] PGAOUT - connected (opt filtered) to ADCIN
+ : PCB footprints for RC filter or short-to-ADCIN
+ [_] PGAREF - set to Vanalog/2 for signed codes
+ : switchable between gnd and Vref/2
+ [_] 0% ADC1 - on cc430
+ : pins shared with
+ : ref gen in/out
+ : comparator
+ : timerA1
+ : RTC clock out
+ : SVM supply V monitor flag
+ x - biasp
+ x - biasccp
+ x - buf_biasp
+ x - buf_biasccp
+ x - arb_out0 ??
+ x - arb_out1 ??
+ - Idvdd_430
+ - Ivdd_430
+ - Ivdd_atoi
+ - Iavdd
+ [_] 0% DAC0 - shared SPI bus
+ : DAC8568 (sampled from TI)
+ : TSSOP-16
+ : 8ch 16bit 2.7 Vmin
+ : 2.5 Vref
+ [_] 0% Control
+ [_] SPI1 on ns430
+ [_] USCI_A0 or USCI_B0 on cc430
+ [_] 0% Output Signals
+ [_] x - biasR tuning
+ [_] x - buf_biasR tuning
+ [_] x -
+ [_] x -
+ [_] x -
+ [_] x -
+ [_] x -
+ [_] x -
+ [_] 0% Pins
+ [_] 1 - /LDAC - load DACs
+ [_] 2 - /SYNC - SPI /CS - frame sync input data
+ [_] 3 - AVDD
+ [_] 4 - VoutA
+ [_] 5 - VoutC
+ [_] 6 - VoutE
+ [_] 7 - VoutG
+ [_] 8 - VrefIN/VrefOUT - 2.5 V reference internal/external
+ [_] 9 - /CLR - async clear input
+ [_] 10- VoutH
+ [_] 11- VoutF
+ [_] 12- VoutD
+ [_] 13- VoutB
+ [_] 14- GND
+ [_] 15- DIN - SPI MOSI
+ [_] 16- SCLK - SPI clock
+ [_] 0% DigiPot0 - shared I2C bus
+ : AD5242 (sampled from ADI)
+ : 1M 256tap I2C pot 2.7 Vmin
+ : TSSOP-16
+ [_] 0% Control
+ [_] I2C on ns430
+ [_] USCI_B0 on cc430
+ [_] 0% Pot1
+ [_] A1 - open, test point
+ [_] W1 - biasR pin, ADC in
+ [_] B1 - 1k top, ADC in
+ : 1k bottom to AGND
+ [_] 0% Pot2
+ [_] A2 - open, test point
+ [_] W2 - buf_biasR pin, ADC in
+ [_] B2 - 1k top, ADC in
+ : 1k bottom to AGND
+ [_] 0% Pins
+ [_] 1 - O1 - logic out1
+ [_] 2 - A1 - pot1 top
+ [_] 3 - W1 - pot1 wiper
+ [_] 4 - B1 - pot1 bottom
+ [_] 5 - VDD - 2.2-5.5V
+ [_] 6 - /SHDN - async short W-B, tie to VDD
+ [_] 7 - SCL - I2C clock
+ [_] 8 - SDA - I2C data
+ [_] 9 - AD0 - I2C address0
+ [_] 10- AD1 - I2C address1
+ [_] 11- DGND - logic common
+ [_] 12- VSS - lowest Vpot - (-2.7-0V)
+ [_] 13- O2 - logic out2
+ [_] 14- B2 - pot2 bottom
+ [_] 15- W2 - pot2 wiper
+ [_] 16- A2 - pot2 top
+
projects / 430.git / commitdiff