-class DAC_Channel(object):
- def __init__(self, defaults):
- self._value = defaults['value']
- @property
- def value(self):
- return self._value
-class DAC_word(object):
- """
- Container for (easily) constructing an appropriate 32-bit DAC8568 command.
- """
+class DAC8568(object):
+ CTL_WIDTH = 32
+ DAC_WIDTH = 16
+ POR_VALUE = 2**(DAC_WIDTH - 1)
+
ALL_CHANNELS = 0xf
- def __init__(self):
- self._word = intbv(0)[32:]
+ # Clear Code Register values
+ CLEAR_TO_ZERO = 0
+ CLEAR_TO_MID = 1
+ CLEAR_TO_FULL = 2
+ IGNORE_CLR = 3
+
+ # DAC channel writing modes
+ INPUT = 0
+ UPDATE = 1
+ INPUT_UPDATE_ALL = 2
+ INPUT_UPDATE_SINGLE = 3
+
+ # channel power modes
+ POWER_ON = 0
+ POWER_OFF_1k = 1
+ POWER_OFF_100k = 2
+ POWER_OFF_HIZ = 3
+
+ # internal reference modes
+ REF_STATIC_OFF = 0x08000000
+ REF_STATIC_ON = 0x08000001
+ REF_FLEXIBLE_ON = 0x09080000
+ REF_FLEXIBLE_ALWAYS_ON = 0x090a0000
+ REF_FLEXIBLE_ALWAYS_OFF = 0x090c0000
+ REF_TO_STATIC_MODE = 0x09000000
+
+ def __init__(self, spibus, cs='dac'):
+ self.bus = spibus
+ self.cs = 'dac'
+ self._word = intbv(0)[self.CTL_WIDTH:]
+
+ def __str__(self):
+ return ''.join(map(chr, self.bytes()))
@property
def word(self):
return self._word
- #prefix bits are 0xxx always
- #def prefix(self, value):
- # self._word[32:28] = intbv(value, max=2**4)
-
- def control(self, value):
- self._word[28:24] = intbv(value, max=2**4)
-
- def address(self, value):
- self._word[24:20] = intbv(value, max=2**4)
-
- def data(self, value):
- self._word[20:4] = intbv(value, max=2**16)
-
- def feature(self, value):
- self._word[4:0] = intbv(value, max=2**4)
+ def CCR(self, mode):
+ self._clear()
+ self._control(0x5)
+ self._feature(mode)
def LDAC(self, bitfield):
- self.reset()
- self.control(0x6)
+ self._clear()
+ self._control(0x6)
self._word[8:0] = intbv(bitfield, max=2**8)
- def reset(self):
- self._word = intbv(0)[32:]
-
+ def swreset(self):
+ self._clear()
+ self._control(0x7)
-class DAC8568(object):
- CTL_WIDTH = 32
- DAC_WIDTH = 16
- POR_VALUE = 2**(DAC_WIDTH - 1)
+ def set(self, addr, value, mode):
+ self._clear()
+ self._control(mode)
+ self._address(addr)
+ self._data(value)
- def __init__(self, spibus, cs='dac'):
- self.bus = spibus
- self.cs = 'dac'
- self._word = intbv(0)[self.CTL_WIDTH:]
-
- def __str__(self):
- return ''.join(map(chr, self.bytes()))
+ def power(self, mode, bitfield):
+ self._clear()
+ self._control(0x4)
+ self._word[10:8] = intbv(mode, max=2**2)
+ self._word[8:0] = intbv(bitfield, max=2**8)
- def updateall(self, value):
- v = intbv(value, max=self.DAC_WIDTH)
- d = intbv(0)[32:]
- d[28:24] = 0x3
- d[24:20] = 0xf
- d += (v << 4)
+ def reference(self, mode):
+ self._clear()
+ self._word = intbv(mode, max=2**32)
def bytes(self):
"""Return the control data as a byte sequence in MSB..LSB order."""
self.bus.Start()
self.bus.Write(str(self))
self.bus.Stop()
+
+ #
+ # internal functions to help construct a command
+ #
+ def _clear(self):
+ self._word = intbv(0)[32:]
+
+ def _control(self, value):
+ self._word[28:24] = intbv(value, max=2**4)
+
+ def _address(self, value):
+ #other values are no-op addresses
+ if (value <= 7) or (value == 15):
+ self._word[24:20] = intbv(value, max=2**4)
+
+ def _data(self, value):
+ self._word[20:4] = intbv(value, max=2**16)
+
+ def _feature(self, value):
+ self._word[4:0] = intbv(value, max=2**4)