Work on schematic

diff --git a/test-pcb/atoi-1.sch b/test-pcb/atoi-1.sch
index 8ece6e0a0b475ce6e48e94a6e0039b667597c15b..369de76a75c5f9949564dfb0d31de1dfe7049b70 100644 (file)
--- a/test-pcb/atoi-1.sch
+++ b/test-pcb/atoi-1.sch
@@ -6,26 +6,470 @@ refdes=U?
 T 46000 57100 5 10 1 1 0 3 1
 footprint=SEMPAC_12x12_100A.fp
 }
-C 59700 61700 1 0 0 ad5242-1.sym
+C 20900 51700 1 0 0 cc430f5137-1.sym
 {
-T 61500 69200 5 10 0 0 0 0 1
-footprint=QFN_24N__ADI
-T 60800 67900 5 10 1 1 0 3 1
+T 25000 65700 5 10 1 1 0 3 1
 refdes=U?
+T 25000 64900 5 10 1 1 0 3 1
+footprint=QFN_48N__TI.fp
+T 25000 64500 5 10 1 1 0 3 1
+document=cc430f5137.pdf
+}
+C 60600 63100 1 0 0 resistor-3.sym
+{
+T 57200 63900 5 10 0 0 0 0 1
+device=RESISTOR
+T 60900 63700 5 10 1 1 0 0 1
+refdes=R?
+T 60900 63400 5 10 1 1 0 0 1
+value=1k
+}
+C 55000 66800 1 0 0 generic-power.sym
+{
+T 55200 67050 5 10 1 1 0 3 1
+net=Vcc:1
+}
+C 60600 62800 1 0 0 gnd-1.sym
+{
+T 60500 62650 5 10 1 1 0 0 1
+net=AVSS
+}
+C 56500 62700 1 0 1 resistor-3.sym
+{
+T 56200 63300 5 10 1 1 0 6 1
+refdes=R?
+T 56200 63000 5 10 1 1 0 6 1
+value=1k
+}
+C 56500 62400 1 0 1 gnd-1.sym
+{
+T 56600 62250 5 10 1 1 0 6 1
+net=AVSS
+}
+C 57400 55400 1 0 0 EMBEDDEDdac8568-1.sym
+[
+B 57700 55700 2300 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+V 57650 59300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 57400 59300 57600 59300 1 0 0
+{
+T 57750 59300 9 10 1 1 0 1 1
+pinlabel=\_LDAC\_
+T 57600 59350 5 8 1 1 0 6 1
+pinnumber=1
+T 57600 59350 5 8 0 1 0 6 1
+pinseq=1
+T 57600 59350 9 10 0 1 0 6 1
+pintype=in
+}
+V 57650 58900 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 57400 58900 57600 58900 1 0 0
+{
+T 57750 58900 9 10 1 1 0 1 1
+pinlabel=\_SYNC\_
+T 57600 58950 5 8 1 1 0 6 1
+pinnumber=2
+T 57600 58950 5 8 0 1 0 6 1
+pinseq=2
+T 57600 58950 9 10 0 1 0 6 1
+pintype=in
+}
+P 58900 60500 58900 60200 1 0 0
+{
+T 58900 60150 9 10 1 1 90 7 1
+pinlabel=AVDD
+T 58950 60250 5 8 1 1 0 0 1
+pinnumber=3
+T 58950 60250 5 8 0 1 0 0 1
+pinseq=3
+T 58800 55450 9 10 0 1 0 6 1
+pintype=pwr
+}
+P 57400 58100 57700 58100 1 0 0
+{
+T 57750 58100 9 10 1 1 0 1 1
+pinlabel=Vout0
+T 57600 58150 5 8 1 1 0 6 1
+pinnumber=4
+T 57600 58150 5 8 0 1 0 6 1
+pinseq=4
+T 57600 58150 9 10 0 1 0 6 1
+pintype=out
+}
+P 57400 57700 57700 57700 1 0 0
+{
+T 57750 57700 9 10 1 1 0 1 1
+pinlabel=Vout2
+T 57600 57750 5 8 1 1 0 6 1
+pinnumber=5
+T 57600 57750 5 8 0 1 0 6 1
+pinseq=5
+T 57600 57750 9 10 0 1 0 6 1
+pintype=out
+}
+P 57400 57300 57700 57300 1 0 0
+{
+T 57750 57300 9 10 1 1 0 1 1
+pinlabel=Vout4
+T 57600 57350 5 8 1 1 0 6 1
+pinnumber=6
+T 57600 57350 5 8 0 1 0 6 1
+pinseq=6
+T 57600 57350 9 10 0 1 0 6 1
+pintype=out
+}
+P 57400 56900 57700 56900 1 0 0
+{
+T 57750 56900 9 10 1 1 0 1 1
+pinlabel=Vout6
+T 57600 56950 5 8 1 1 0 6 1
+pinnumber=7
+T 57600 56950 5 8 0 1 0 6 1
+pinseq=7
+T 57600 56950 9 10 0 1 0 6 1
+pintype=out
 }
-C 58200 51400 1 0 0 ads8201-1.sym
+P 57400 56100 57700 56100 1 0 0
 {
-T 61500 58700 5 10 0 0 0 0 1
+T 57750 56100 9 10 1 1 0 1 1
+pinlabel=Vref
+T 57600 56150 5 8 1 1 0 6 1
+pinnumber=8
+T 57600 56150 5 8 0 1 0 6 1
+pinseq=8
+T 57600 56150 9 10 0 1 0 6 1
+pintype=out
+}
+V 60050 56100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 60300 56100 60100 56100 1 0 0
+{
+T 59950 56100 9 10 1 1 0 7 1
+pinlabel=\_CLR\_
+T 60100 56150 5 8 1 1 0 0 1
+pinnumber=9
+T 60100 56150 5 8 0 1 0 0 1
+pinseq=9
+T 59900 56150 9 10 0 1 0 6 1
+pintype=in
+}
+P 60300 56900 60000 56900 1 0 0
+{
+T 59950 56900 9 10 1 1 0 7 1
+pinlabel=Vout7
+T 60100 56950 5 8 1 1 0 0 1
+pinnumber=10
+T 60100 56950 5 8 0 1 0 0 1
+pinseq=10
+T 59900 56950 9 10 0 1 0 6 1
+pintype=out
+}
+P 60300 57300 60000 57300 1 0 0
+{
+T 59950 57300 9 10 1 1 0 7 1
+pinlabel=Vout5
+T 60100 57350 5 8 1 1 0 0 1
+pinnumber=11
+T 60100 57350 5 8 0 1 0 0 1
+pinseq=11
+T 59900 57350 9 10 0 1 0 6 1
+pintype=out
+}
+P 60300 57700 60000 57700 1 0 0
+{
+T 59950 57700 9 10 1 1 0 7 1
+pinlabel=Vout3
+T 60100 57750 5 8 1 1 0 0 1
+pinnumber=12
+T 60100 57750 5 8 0 1 0 0 1
+pinseq=12
+T 59900 57750 9 10 0 1 0 6 1
+pintype=out
+}
+P 60300 58100 60000 58100 1 0 0
+{
+T 59950 58100 9 10 1 1 0 7 1
+pinlabel=Vout1
+T 60100 58150 5 8 1 1 0 0 1
+pinnumber=13
+T 60100 58150 5 8 0 1 0 0 1
+pinseq=13
+T 59900 58150 9 10 0 1 0 6 1
+pintype=out
+}
+P 58900 55400 58900 55700 1 0 0
+{
+T 58900 55750 9 10 1 1 90 1 1
+pinlabel=GND
+T 58950 55650 5 8 1 1 0 2 1
+pinnumber=14
+T 58950 55650 5 8 0 1 0 2 1
+pinseq=14
+T 58800 55850 9 10 0 1 0 6 1
+pintype=pwr
+}
+P 60300 58900 60000 58900 1 0 0
+{
+T 59950 58900 9 10 1 1 0 7 1
+pinlabel=DIN
+T 60100 58950 5 8 1 1 0 0 1
+pinnumber=15
+T 60100 58950 5 8 0 1 0 0 1
+pinseq=15
+T 59900 58950 9 10 0 1 0 6 1
+pintype=in
+}
+P 60300 59300 60000 59300 1 0 0
+{
+T 59950 59300 9 10 1 1 0 7 1
+pinlabel=SCLK
+T 60100 59350 5 8 1 1 0 0 1
+pinnumber=16
+T 60100 59350 5 8 0 1 0 0 1
+pinseq=16
+T 59900 59350 9 10 0 1 0 6 1
+pintype=in
+}
+T 60000 60300 9 10 0 0 0 0 1
+document=dac8586.pdf
+T 60000 60500 9 10 0 0 0 0 1
+footprint=TSSOP_16N__TI
+T 58900 59100 9 10 0 1 0 3 1
+refdes=U?
+T 58900 58700 9 10 1 1 0 3 1
+DAC8568
+]
+{
+T 59900 53400 5 10 0 0 0 0 1
+footprint=TSSOP_16N__TI
+T 58900 59100 5 10 1 1 0 3 1
+refdes=U?
+}
+C 56800 48400 1 0 0 ads8201-1.sym
+{
+T 59700 53200 5 10 0 0 0 0 1
 footprint=QFN_24N__TI
-T 60000 57200 5 10 1 1 0 3 1
+T 58400 51600 5 10 1 1 0 3 1
 refdes=U?
 }
-C 20900 51700 1 0 0 cc430f5137-1.sym
+C 57600 60700 1 0 0 ad5242-1.sym
 {
-T 25000 65700 5 10 1 1 0 3 1
+T 61500 60500 5 10 0 0 0 0 1
+footprint=QFN_24N__ADI
+T 58700 64800 5 10 1 1 0 3 1
 refdes=U?
-T 25000 64900 5 10 1 1 0 3 1
-footprint=QFN_48N__TI.fp
-T 25000 64500 5 10 1 1 0 3 1
-document=cc430f5137.pdf
 }
+C 55800 62700 1 0 1 resistor-3.sym
+{
+T 55500 63300 5 10 1 1 0 6 1
+refdes=R?
+T 55500 63000 5 10 1 1 0 6 1
+value=1k
+}
+C 61300 63100 1 0 0 resistor-3.sym
+{
+T 61600 63700 5 10 1 1 0 0 1
+refdes=R?
+T 61600 63400 5 10 1 1 0 0 1
+value=1k
+}
+C 51400 60200 1 0 0 gnd-1.sym
+{
+T 51600 60350 5 10 1 1 0 0 1
+net=AVSS
+}
+N 51500 60500 50800 60500 4
+N 50800 60500 50800 60100 4
+N 55800 64200 57600 64200 4
+{
+T 57100 64200 5 10 1 1 0 0 1
+netname=biasR
+}
+N 52300 57300 53400 57300 4
+{
+T 52500 57300 5 10 1 1 0 0 1
+netname=biasR
+}
+N 59700 64600 61800 64600 4
+{
+T 59800 64600 5 10 1 1 0 0 1
+netname=buf_biasR
+}
+C 59900 64800 1 0 0 pad-r.sym
+{
+T 60200 65200 5 10 1 1 0 0 1
+refdes=pad?
+}
+C 56200 64400 1 0 0 pad-l.sym
+{
+T 56700 64800 5 10 1 1 0 0 1
+refdes=pad?
+}
+N 57400 64600 57600 64600 4
+N 59900 65000 59700 65000 4
+N 60700 64000 60700 64200 4
+N 56400 63600 56400 63800 4
+N 55700 58100 55700 62700 4
+N 55700 58100 57400 58100 4
+N 61400 58100 60300 58100 4
+N 57400 57700 56500 57700 4
+{
+T 56700 57700 5 10 1 1 0 0 1
+netname=INA
+}
+N 60300 57700 61300 57700 4
+{
+T 60700 57700 5 10 1 1 0 0 1
+netname=INB
+}
+N 52300 55700 53400 55700 4
+{
+T 52500 55700 5 10 1 1 0 0 1
+netname=INA
+}
+N 52300 55300 53400 55300 4
+{
+T 52500 55300 5 10 1 1 0 0 1
+netname=INB
+}
+N 52300 54900 53400 54900 4
+{
+T 52500 54900 5 10 1 1 0 0 1
+netname=CMI
+}
+C 53000 63600 1 0 1 opamp-dual-1.sym
+{
+T 53900 64300 5 10 0 0 0 6 1
+device=DUAL_OPAMP
+T 52800 64500 5 10 1 1 0 6 1
+refdes=U?
+T 52300 64300 5 10 1 0 0 6 1
+slot=2
+T 53400 62900 5 10 0 1 0 6 1
+footprint=SOT23__Maxim
+T 53900 64500 5 10 0 0 0 6 1
+symversion=0.2
+T 52300 63700 5 10 1 1 0 6 1
+value=MAX9912
+T 53400 62700 5 10 0 0 0 6 1
+slot=2
+}
+C 55800 64000 1 0 1 opamp-dual-1.sym
+{
+T 53700 65900 5 10 0 0 0 6 1
+device=DUAL_OPAMP
+T 55600 64900 5 10 1 1 0 6 1
+refdes=U?
+T 55100 64700 5 10 1 0 0 6 1
+slot=1
+T 53200 64500 5 10 0 1 0 6 1
+footprint=SOT23__Maxim
+T 53700 66100 5 10 0 0 0 6 1
+symversion=0.2
+T 55100 64100 5 10 1 1 0 6 1
+value=MAX9912
+}
+N 53400 64400 54800 64400 4
+{
+T 53500 64500 5 10 1 1 0 0 1
+netname=ADC0_IN0
+}
+N 54500 64400 54500 65200 4
+N 54500 65200 55800 65200 4
+N 55800 65200 55800 64600 4
+N 53000 64200 53000 64800 4
+N 51700 64800 53000 64800 4
+N 51700 64000 51700 64800 4
+N 50700 64000 52000 64000 4
+{
+T 50800 64100 5 10 1 1 0 0 1
+netname=ADC0_IN1
+}
+N 53000 63800 57600 63800 4
+N 55700 63800 55700 63600 4
+N 59700 64200 64600 64200 4
+N 61400 64000 61400 64200 4
+C 64600 64000 1 0 0 opamp-dual-1.sym
+{
+T 64800 64900 5 10 1 1 0 0 1
+refdes=U?
+T 65300 64700 5 10 1 0 0 0 1
+slot=2
+T 65300 64100 5 10 1 1 0 0 1
+value=MAX9912
+}
+C 61800 64400 1 0 0 opamp-dual-1.sym
+{
+T 62000 65300 5 10 1 1 0 0 1
+refdes=U?
+T 62500 65100 5 10 1 0 0 0 1
+slot=1
+T 62500 64500 5 10 1 1 0 0 1
+value=MAX9912
+}
+N 62800 64800 64200 64800 4
+{
+T 63300 64900 5 10 1 1 0 0 1
+netname=ADC0_IN2
+}
+N 63100 64800 63100 65600 4
+N 63100 65600 61800 65600 4
+N 61800 65600 61800 65000 4
+N 64600 64600 64600 65200 4
+N 65900 65200 64600 65200 4
+N 65900 64400 65900 65200 4
+N 65600 64400 67000 64400 4
+{
+T 66100 64500 5 10 1 1 0 0 1
+netname=ADC0_IN3
+}
+N 61400 63100 61400 58100 4
+N 58600 53200 58600 54200 4
+{
+T 58600 53300 5 10 1 1 90 0 1
+netname=ADC0_IN0
+}
+N 58200 53200 58200 54200 4
+{
+T 58200 53300 5 10 1 1 90 0 1
+netname=ADC0_IN1
+}
+N 57800 53200 57800 54200 4
+{
+T 57800 53300 5 10 1 1 90 0 1
+netname=ADC0_IN2
+}
+N 57400 53200 57400 54200 4
+{
+T 57400 53300 5 10 1 1 90 0 1
+netname=ADC0_IN3
+}
+N 52300 56100 53400 56100 4
+{
+T 52500 56100 5 10 1 1 0 0 1
+netname=buf_biasR
+}
+C 57300 62100 1 0 1 resistor-3.sym
+{
+T 57000 62700 5 10 1 1 0 6 1
+refdes=R?
+T 57000 62400 5 10 1 1 0 6 1
+value=1k
+}
+N 57600 63000 57200 63000 4
+N 57200 62100 57600 62100 4
+N 57600 62100 57600 62600 4
+C 59900 60900 1 0 0 gnd-1.sym
+{
+T 59800 60750 5 10 1 1 0 0 1
+net=AVSS
+}
+N 59700 63000 60000 63000 4
+N 60000 61200 60000 63000 4
+N 60000 62600 59700 62600 4
+C 57200 63200 1 0 0 generic-power.sym
+{
+T 57400 63450 5 10 1 1 0 3 1
+net=VddPA:1
+}
+N 57400 63200 57400 63000 4
+N 59700 61800 60000 61800 4
+N 59700 61400 60000 61400 4

diff --git a/test-pcb/gafrc-libraries b/test-pcb/gafrc-libraries
index 846c493df0a916f46acff56db3693b624bbc7d33..ca23a9e88233f1ead8fd281f1003d18a9f19b37b 100644 (file)
--- a/test-pcb/gafrc-libraries
+++ b/test-pcb/gafrc-libraries
@@ -1,4 +1,7 @@
 (component-library "./sym")
 (component-library ".")
+(component-library "/home/dan/wa/gaf/sym/analog")
+(component-library "/home/dan/wa/gaf/sym/passive")
+(component-library "/home/dan/wa/gaf/sym/power")
 
 (source-library ".")

diff --git a/test-pcb/sym/ad5242-1.djboxsym b/test-pcb/sym/ad5242-1.djboxsym
index d454ce7faa3f05c5cef1d455af336065bbbf115b..c43a5a466b7eb14c64bd34cdd2dfa37f397d3935 100644 (file)
--- a/test-pcb/sym/ad5242-1.djboxsym
+++ b/test-pcb/sym/ad5242-1.djboxsym
@@ -1,5 +1,4 @@
 
---vmode
 
 [labels]
 refdes=U?
@@ -8,33 +7,31 @@ AD5242
 ! document=ad5242.pdf
 
 [left]
+1      o       O1
 2              A1
 3              W1
 4              B1
 
-16             A2
-15             W2
-14             B2
-
+5      p       VDD
 6      !i      \_SHDN\_
 
 7      i       SCL
 8      io      SDA
 
-9      i       AD0
-10     i       AD1
+
 
 [right]
-1      o       O1
-.skip 1200
+16             A2
+15             W2
+14             B2
 13     o       O2
 
-[top]
-5      p       VDD
+12     p       VSS
+11     p       DGND
+
+10     i       AD1
+9      i       AD0
 
 
-[bottom]
-11     p       DGND
-12     p       VSS
 
 # vim:softtabstop=0 noexpandtab ft=sh

diff --git a/test-pcb/sym/ad5242-1.sym b/test-pcb/sym/ad5242-1.sym
index 8a383c84a6b47d87ab22455219c14d6c3f08aba0..df1a7aa4a06823a22917e2456bf3ac75d55b8ea3 100644 (file)
--- a/test-pcb/sym/ad5242-1.sym
+++ b/test-pcb/sym/ad5242-1.sym
@@ -1,187 +1,187 @@
 v 20060123 1
-B 300 300 1500 6900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-T 1800 7300 9 10 0 0 0 0 1
+B 300 300 1500 4400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 1800 4800 9 10 0 0 0 0 1
 document=ad5242.pdf
-T 1800 7500 9 10 0 0 0 0 1
+T 1800 5000 9 10 0 0 0 0 1
 footprint=QFN_24N__ADI
-T 1100 6200 9 10 1 1 0 3 1
+T 1100 4100 9 10 1 1 0 3 1
 refdes=U?
-T 1100 5800 9 10 1 1 0 3 1
+T 1100 3700 9 10 1 1 0 3 1
 AD5242
-P 2100 6400 1800 6400 1 0 0
+P 0 4300 300 4300 1 0 0
 {
-T 1750 6400 9 10 1 1 0 7 1
+T 350 4300 9 10 1 1 0 1 1
 pinlabel=O1
-T 1900 6450 5 8 1 1 0 0 1
+T 200 4350 5 8 1 1 0 6 1
 pinnumber=1
-T 1900 6450 5 8 0 1 0 0 1
+T 200 4350 5 8 0 1 0 6 1
 pinseq=1
-T 1700 6450 9 10 0 1 0 6 1
+T 200 4350 9 10 0 1 0 6 1
 pintype=out
 }
-P 0 6400 300 6400 1 0 0
+P 0 3900 300 3900 1 0 0
 {
-T 350 6400 9 10 1 1 0 1 1
+T 350 3900 9 10 1 1 0 1 1
 pinlabel=A1
-T 200 6450 5 8 1 1 0 6 1
+T 200 3950 5 8 1 1 0 6 1
 pinnumber=2
-T 200 6450 5 8 0 1 0 6 1
+T 200 3950 5 8 0 1 0 6 1
 pinseq=2
-T 200 6450 9 10 0 1 0 6 1
+T 200 3950 9 10 0 1 0 6 1
 pintype=pas
 }
-P 0 6000 300 6000 1 0 0
+P 0 3500 300 3500 1 0 0
 {
-T 350 6000 9 10 1 1 0 1 1
+T 350 3500 9 10 1 1 0 1 1
 pinlabel=W1
-T 200 6050 5 8 1 1 0 6 1
+T 200 3550 5 8 1 1 0 6 1
 pinnumber=3
-T 200 6050 5 8 0 1 0 6 1
+T 200 3550 5 8 0 1 0 6 1
 pinseq=3
-T 200 6050 9 10 0 1 0 6 1
+T 200 3550 9 10 0 1 0 6 1
 pintype=pas
 }
-P 0 5600 300 5600 1 0 0
+P 0 3100 300 3100 1 0 0
 {
-T 350 5600 9 10 1 1 0 1 1
+T 350 3100 9 10 1 1 0 1 1
 pinlabel=B1
-T 200 5650 5 8 1 1 0 6 1
+T 200 3150 5 8 1 1 0 6 1
 pinnumber=4
-T 200 5650 5 8 0 1 0 6 1
+T 200 3150 5 8 0 1 0 6 1
 pinseq=4
-T 200 5650 9 10 0 1 0 6 1
+T 200 3150 9 10 0 1 0 6 1
 pintype=pas
 }
-P 1100 7500 1100 7200 1 0 0
+P 0 2300 300 2300 1 0 0
 {
-T 1100 7150 9 10 1 1 90 7 1
+T 350 2300 9 10 1 1 0 1 1
 pinlabel=VDD
-T 1150 7250 5 8 1 1 0 0 1
+T 200 2350 5 8 1 1 0 6 1
 pinnumber=5
-T 1150 7250 5 8 0 1 0 0 1
+T 200 2350 5 8 0 1 0 6 1
 pinseq=5
-T 1000 50 9 10 0 1 0 6 1
+T 200 2350 9 10 0 1 0 6 1
 pintype=pwr
 }
-V 250 3200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-P 0 3200 200 3200 1 0 0
+V 250 1900 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 0 1900 200 1900 1 0 0
 {
-T 350 3200 9 10 1 1 0 1 1
+T 350 1900 9 10 1 1 0 1 1
 pinlabel=\_SHDN\_
-T 200 3250 5 8 1 1 0 6 1
+T 200 1950 5 8 1 1 0 6 1
 pinnumber=6
-T 200 3250 5 8 0 1 0 6 1
+T 200 1950 5 8 0 1 0 6 1
 pinseq=6
-T 200 3250 9 10 0 1 0 6 1
+T 200 1950 9 10 0 1 0 6 1
 pintype=in
 }
-P 0 2400 300 2400 1 0 0
+P 0 1100 300 1100 1 0 0
 {
-T 350 2400 9 10 1 1 0 1 1
+T 350 1100 9 10 1 1 0 1 1
 pinlabel=SCL
-T 200 2450 5 8 1 1 0 6 1
+T 200 1150 5 8 1 1 0 6 1
 pinnumber=7
-T 200 2450 5 8 0 1 0 6 1
+T 200 1150 5 8 0 1 0 6 1
 pinseq=7
-T 200 2450 9 10 0 1 0 6 1
+T 200 1150 9 10 0 1 0 6 1
 pintype=in
 }
-P 0 2000 300 2000 1 0 0
+P 0 700 300 700 1 0 0
 {
-T 350 2000 9 10 1 1 0 1 1
+T 350 700 9 10 1 1 0 1 1
 pinlabel=SDA
-T 200 2050 5 8 1 1 0 6 1
+T 200 750 5 8 1 1 0 6 1
 pinnumber=8
-T 200 2050 5 8 0 1 0 6 1
+T 200 750 5 8 0 1 0 6 1
 pinseq=8
-T 200 2050 9 10 0 1 0 6 1
+T 200 750 9 10 0 1 0 6 1
 pintype=inout
 }
-P 0 1200 300 1200 1 0 0
+P 2100 700 1800 700 1 0 0
 {
-T 350 1200 9 10 1 1 0 1 1
+T 1750 700 9 10 1 1 0 7 1
 pinlabel=AD0
-T 200 1250 5 8 1 1 0 6 1
+T 1900 750 5 8 1 1 0 0 1
 pinnumber=9
-T 200 1250 5 8 0 1 0 6 1
+T 1900 750 5 8 0 1 0 0 1
 pinseq=9
-T 200 1250 9 10 0 1 0 6 1
+T 1700 750 9 10 0 1 0 6 1
 pintype=in
 }
-P 0 800 300 800 1 0 0
+P 2100 1100 1800 1100 1 0 0
 {
-T 350 800 9 10 1 1 0 1 1
+T 1750 1100 9 10 1 1 0 7 1
 pinlabel=AD1
-T 200 850 5 8 1 1 0 6 1
+T 1900 1150 5 8 1 1 0 0 1
 pinnumber=10
-T 200 850 5 8 0 1 0 6 1
+T 1900 1150 5 8 0 1 0 0 1
 pinseq=10
-T 200 850 9 10 0 1 0 6 1
+T 1700 1150 9 10 0 1 0 6 1
 pintype=in
 }
-P 900 0 900 300 1 0 0
+P 2100 1900 1800 1900 1 0 0
 {
-T 900 350 9 10 1 1 90 1 1
+T 1750 1900 9 10 1 1 0 7 1
 pinlabel=DGND
-T 950 250 5 8 1 1 0 2 1
+T 1900 1950 5 8 1 1 0 0 1
 pinnumber=11
-T 950 250 5 8 0 1 0 2 1
+T 1900 1950 5 8 0 1 0 0 1
 pinseq=11
-T 800 550 9 10 0 1 0 6 1
+T 1700 1950 9 10 0 1 0 6 1
 pintype=pwr
 }
-P 1300 0 1300 300 1 0 0
+P 2100 2300 1800 2300 1 0 0
 {
-T 1300 350 9 10 1 1 90 1 1
+T 1750 2300 9 10 1 1 0 7 1
 pinlabel=VSS
-T 1350 250 5 8 1 1 0 2 1
+T 1900 2350 5 8 1 1 0 0 1
 pinnumber=12
-T 1350 250 5 8 0 1 0 2 1
+T 1900 2350 5 8 0 1 0 0 1
 pinseq=12
-T 1200 550 9 10 0 1 0 6 1
+T 1700 2350 9 10 0 1 0 6 1
 pintype=pwr
 }
-P 2100 4800 1800 4800 1 0 0
+P 2100 3100 1800 3100 1 0 0
 {
-T 1750 4800 9 10 1 1 0 7 1
+T 1750 3100 9 10 1 1 0 7 1
 pinlabel=O2
-T 1900 4850 5 8 1 1 0 0 1
+T 1900 3150 5 8 1 1 0 0 1
 pinnumber=13
-T 1900 4850 5 8 0 1 0 0 1
+T 1900 3150 5 8 0 1 0 0 1
 pinseq=13
-T 1700 4850 9 10 0 1 0 6 1
+T 1700 3150 9 10 0 1 0 6 1
 pintype=out
 }
-P 0 4000 300 4000 1 0 0
+P 2100 3500 1800 3500 1 0 0
 {
-T 350 4000 9 10 1 1 0 1 1
+T 1750 3500 9 10 1 1 0 7 1
 pinlabel=B2
-T 200 4050 5 8 1 1 0 6 1
+T 1900 3550 5 8 1 1 0 0 1
 pinnumber=14
-T 200 4050 5 8 0 1 0 6 1
+T 1900 3550 5 8 0 1 0 0 1
 pinseq=14
-T 200 4050 9 10 0 1 0 6 1
+T 1700 3550 9 10 0 1 0 6 1
 pintype=pas
 }
-P 0 4400 300 4400 1 0 0
+P 2100 3900 1800 3900 1 0 0
 {
-T 350 4400 9 10 1 1 0 1 1
+T 1750 3900 9 10 1 1 0 7 1
 pinlabel=W2
-T 200 4450 5 8 1 1 0 6 1
+T 1900 3950 5 8 1 1 0 0 1
 pinnumber=15
-T 200 4450 5 8 0 1 0 6 1
+T 1900 3950 5 8 0 1 0 0 1
 pinseq=15
-T 200 4450 9 10 0 1 0 6 1
+T 1700 3950 9 10 0 1 0 6 1
 pintype=pas
 }
-P 0 4800 300 4800 1 0 0
+P 2100 4300 1800 4300 1 0 0
 {
-T 350 4800 9 10 1 1 0 1 1
+T 1750 4300 9 10 1 1 0 7 1
 pinlabel=A2
-T 200 4850 5 8 1 1 0 6 1
+T 1900 4350 5 8 1 1 0 0 1
 pinnumber=16
-T 200 4850 5 8 0 1 0 6 1
+T 1900 4350 5 8 0 1 0 0 1
 pinseq=16
-T 200 4850 9 10 0 1 0 6 1
+T 1700 4350 9 10 0 1 0 6 1
 pintype=pas
 }

diff --git a/test-pcb/sym/ads8201-1.djboxsym b/test-pcb/sym/ads8201-1.djboxsym
index 73cef78a71ddde006b0c1b06fd64545b26205caf..0c3c977d0522acfb693b64694fe631491ad77f5a 100644 (file)
--- a/test-pcb/sym/ads8201-1.djboxsym
+++ b/test-pcb/sym/ads8201-1.djboxsym
@@ -15,6 +15,7 @@ ADS8201
 
 5      i!      \_RST\_
 6      o       BUSY/INT
+.skip 400
 
 
 [right]
@@ -25,6 +26,7 @@ ADS8201
 15     p       REF
 14     p       VDDA
 13     p       VDDIO
+.skip 400
 
 
 [top]

diff --git a/test-pcb/sym/pad-l.sym b/test-pcb/sym/pad-l.sym
new file mode 100644 (file)
index 0000000..7d76b07
--- /dev/null
+++ b/test-pcb/sym/pad-l.sym
@@ -0,0 +1,12 @@
+v 20060123 1
+P 900 200 1200 200 1 0 1
+{
+T 1000 300 5 10 0 1 0 0 1
+pinnumber=1
+T 1000 300 5 10 0 0 0 0 1
+pinseq=1
+}
+T 0 200 8 10 1 1 0 0 1
+refdes=pad?
+V 700 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+V 700 200 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1

diff --git a/test-pcb/sym/pad-r.sym b/test-pcb/sym/pad-r.sym
new file mode 100644 (file)
index 0000000..5572243
--- /dev/null
+++ b/test-pcb/sym/pad-r.sym
@@ -0,0 +1,12 @@
+v 20060123 1
+P 0 200 300 200 1 0 0
+{
+T 100 300 5 10 0 1 0 0 1
+pinnumber=1
+T 100 300 5 10 0 0 0 0 1
+pinseq=1
+}
+T 800 200 8 10 1 1 0 0 1
+refdes=pad?
+V 500 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+V 500 200 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1