--- /dev/null
+#
+# Makefile for msp430
+#
+# 'make' builds everything
+# 'make clean' deletes everything except source files and Makefile
+# You need to set TARGET, MCU and SOURCES for your project.
+# TARGET is the name of the executable file to be produced
+# $(TARGET).elf $(TARGET).hex and $(TARGET).txt nad $(TARGET).map are all generated.
+# The TXT file is used for BSL loading, the ELF can be used for JTAG use
+#
+TARGET = msp4th
+#MCU = msp430f5529
+MCU = msp2
+# List all the source files here
+# eg if you have a source file foo.c then list it here
+SOURCES = x.c
+# Include are located in the Include directory
+#INCLUDES = -IInclude
+INCLUDES = -I.
+# Add or subtract whatever MSPGCC flags you want. There are plenty more
+#######################################################################################
+CFLAGS = -mmcu=$(MCU) -g -Os -Wall -Wunused $(INCLUDES)
+ASFLAGS = -mmcu=$(MCU) -x assembler-with-cpp -Wa,-gstabs
+LDFLAGS = -mmcu=$(MCU) -Wl,-Map=$(TARGET).map
+########################################################################################
+CC = msp430-gcc
+LD = msp430-ld
+AR = msp430-ar
+AS = msp430-gcc
+GASP = msp430-gasp
+NM = msp430-nm
+OBJCOPY = msp430-objcopy
+RANLIB = msp430-ranlib
+STRIP = msp430-strip
+SIZE = msp430-size
+READELF = msp430-readelf
+MAKETXT = srec_cat
+CP = cp -p
+RM = rm -f
+MV = mv
+########################################################################################
+# the file which will include dependencies
+DEPEND = $(SOURCES:.c=.d)
+# all the object files
+OBJECTS = $(SOURCES:.c=.o)
+all: $(TARGET).elf $(TARGET).hex $(TARGET).txt
+$(TARGET).elf: $(OBJECTS)
+ echo "Linking $@"
+ $(CC) $(OBJECTS) $(LDFLAGS) $(LIBS) -o $@
+ echo
+ echo ">>>> Size of Firmware <<<<"
+ $(SIZE) $(TARGET).elf
+ echo
+%.hex: %.elf
+ $(OBJCOPY) -O ihex $< $@
+%.txt: %.hex
+ $(MAKETXT) -O $@ -TITXT $< -I
+ unix2dos $(TARGET).txt
+# The above line is required for the DOS based TI BSL tool to be able to read the txt file generated from linux/unix systems.
+%.o: %.c
+ echo "Compiling $<"
+ $(CC) -c $(CFLAGS) -o $@ $<
+# rule for making assembler source listing, to see the code
+%.lst: %.c
+ $(CC) -c $(ASFLAGS) -Wa,-anlhd $< > $@
+# include the dependencies unless we're going to clean, then forget about them.
+ifneq ($(MAKECMDGOALS), clean)
+-include $(DEPEND)
+endif
+# dependencies file
+# includes also considered, since some of these are our own
+# (otherwise use -MM instead of -M)
+%.d: %.c
+ echo "Generating dependencies $@ from $<"
+ $(CC) -M ${CFLAGS} $< >$@
+.SILENT:
+.PHONY: clean
+clean:
+ -$(RM) $(OBJECTS)
+ -$(RM) $(TARGET).*
+ -$(RM) $(SOURCES:.c=.lst)
+ -$(RM) $(DEPEND)
--- /dev/null
+#ifndef __msp430_headers_adc10_h
+#define __msp430_headers_adc10_h
+
+/* adc10.h
+ *
+ * mspgcc project: MSP430 device headers
+ * ADC10 module header
+ *
+ * (c) 2002 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: adc10.h,v 1.9 2008/10/09 15:00:14 sb-sf Exp $
+ */
+
+/* Switches: none */
+
+#define ADC10DTC0_ 0x0048 /* ADC10 Data Transfer Control 0 */
+sfrb(ADC10DTC0, ADC10DTC0_);
+#define ADC10DTC1_ 0x0049 /* ADC10 Data Transfer Control 1 */
+sfrb(ADC10DTC1, ADC10DTC1_);
+#define ADC10AE0_ 0x004A /* ADC10 Analog Enable */
+sfrb(ADC10AE0, ADC10AE0_);
+
+#if defined(__msp430_have_adc10ae2)
+#define ADC10AE1_ 0x004B /* ADC10 Analog Enable */
+sfrb(ADC10AE1, ADC10AE1_);
+#endif
+
+/* Alternate register names */
+#define ADC10AE_ ADC10AE0_
+#define ADC10AE ADC10AE0
+
+#define ADC10CTL0_ 0x01B0 /* ADC10 Control 0 */
+sfrw(ADC10CTL0, ADC10CTL0_);
+#define ADC10CTL1_ 0x01B2 /* ADC10 Control 1 */
+sfrw(ADC10CTL1, ADC10CTL1_);
+#define ADC10MEM_ 0x01B4 /* ADC10 Memory */
+sfrw(ADC10MEM, ADC10MEM_);
+#define ADC10SA_ 0x01BC /* ADC10 Data Transfer Start Address */
+sfrw(ADC10SA, ADC10SA_);
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+typedef struct {
+ volatile unsigned
+ adc10sc:1,
+ enc:1,
+ adc10ifg:1,
+ adc10ie:1,
+ adc10on:1,
+ refon:1,
+ r2_5v:1,
+ msc:1,
+ adc10sr:4,
+ adc10sht:4;
+} __attribute__ ((packed)) adc10ctl0_t;
+
+typedef struct {
+ volatile unsigned
+ adc10busy:1,
+ conseq:2,
+ adc10ssel:2,
+ adc10div:3;
+} __attribute__ ((packed)) adc10ctl1_t;
+
+/* The adc10 declaration itself */
+struct adc10_t {
+ adc10ctl0_t ctl0;
+ adc10ctl1_t ctl1;
+ volatile unsigned mem;
+ volatile unsigned sa;
+};
+#ifdef __cplusplus
+extern "C" struct adc10_t adc10 asm("0x01B0");
+#else //__cplusplus
+struct adc10_t adc10 asm("0x01B0");
+#endif //__cplusplus
+
+#endif
+
+#define ADC10SC 0x0001 /* ADC10CTL0 */
+#define ENC 0x0002
+#define ADC10IFG 0x0004
+#define ADC10IE 0x0008
+#define ADC10ON 0x0010
+#define REFON 0x0020
+#define REF2_5V 0x0040
+#define MSC 0x0080
+#define REFBURST 0x0100
+#define REFOUT 0x0200
+#define ADC10SR 0x0400
+
+#define ADC10SHT_0 (0<<11) /* 4 x ADC10CLKs */
+#define ADC10SHT_1 (1<<11) /* 8 x ADC10CLKs */
+#define ADC10SHT_2 (2<<11) /* 16 x ADC10CLKs */
+#define ADC10SHT_3 (3<<11) /* 64 x ADC10CLKs */
+
+#define SREF_0 (0<<13) /* VR+ = AVCC and VR- = AVSS */
+#define SREF_1 (1<<13) /* VR+ = VREF+ and VR- = AVSS */
+#define SREF_2 (2<<13) /* VR+ = VEREF+ and VR- = AVSS */
+#define SREF_3 (3<<13) /* VR+ = VEREF+ and VR- = AVSS */
+#define SREF_4 (4<<13) /* VR+ = AVCC and VR- = VREF-/VEREF- */
+#define SREF_5 (5<<13) /* VR+ = VREF+ and VR- = VREF-/VEREF- */
+#define SREF_6 (6<<13) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
+#define SREF_7 (7<<13) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
+
+#define ADC10BUSY 0x0001 /* ADC10CTL1 */
+
+#define CONSEQ_0 (0<<1) /* Single channel single conversion */
+#define CONSEQ_1 (1<<1) /* Sequence of channels */
+#define CONSEQ_2 (2<<1) /* Repeat single channel */
+#define CONSEQ_3 (3<<1) /* Repeat sequence of channels */
+
+#define ADC10SSEL_0 (0<<3) /* ADC10OSC */
+#define ADC10SSEL_1 (1<<3) /* ACLK */
+#define ADC10SSEL_2 (2<<3) /* MCLK */
+#define ADC10SSEL_3 (3<<3) /* SMCLK */
+
+#define ADC10DIV_0 (0<<5)
+#define ADC10DIV_1 (1<<5)
+#define ADC10DIV_2 (2<<5)
+#define ADC10DIV_3 (3<<5)
+#define ADC10DIV_4 (4<<5)
+#define ADC10DIV_5 (5<<5)
+#define ADC10DIV_6 (6<<5)
+#define ADC10DIV_7 (7<<5)
+
+#define ISSH 0x0100
+#define ADC10DF 0x0200
+
+#define SHS_0 (0<<10) /* ADC10SC */
+#define SHS_1 (1<<10) /* TA3 OUT1 */
+#define SHS_2 (2<<10) /* TA3 OUT0 */
+#define SHS_3 (3<<10) /* TA3 OUT2 */
+
+#define INCH_0 (0<<12) /* A0 */
+#define INCH_1 (1<<12) /* A1 */
+#define INCH_2 (2<<12) /* A2 */
+#define INCH_3 (3<<12) /* A3 */
+#define INCH_4 (4<<12) /* A4 */
+#define INCH_5 (5<<12) /* A5 */
+#define INCH_6 (6<<12) /* A6 */
+#define INCH_7 (7<<12) /* A7 */
+#define INCH_8 (8<<12) /* VeREF+ */
+#define INCH_9 (9<<12) /* VREF-/VeREF- */
+#define INCH_10 (10<<12) /* Temperature sensor */
+#define INCH_11 (11<<12) /* (VCC - VSS) / 2 */
+#define INCH_12 (12<<12) /* Selects channel 11 */
+#define INCH_13 (13<<12) /* Selects channel 11 */
+#define INCH_14 (14<<12) /* Selects channel 11 */
+#define INCH_15 (15<<12) /* Selects channel 11 */
+
+#define ADC10FETCH 0x0001 /* ADC10DTC0 */
+#define ADC10B1 0x0002
+#define ADC10CT 0x0004
+#define ADC10TB 0x0008
+
+#define ADC10DISABLE 0x0000 /* ADC10DTC1 */
+
+/* Aliases by mspgcc */
+#define ADC10SHT_DIV4 ADC10SHT_0 /* 4 x ADC10CLKs */
+#define ADC10SHT_DIV8 ADC10SHT_1 /* 8 x ADC10CLKs */
+#define ADC10SHT_DIV16 ADC10SHT_2 /* 16 x ADC10CLKs */
+#define ADC10SHT_DIV64 ADC10SHT_3 /* 64 x ADC10CLKs */
+
+#define SREF_AVCC_AVSS SREF_0 /* VR+ = AVCC and VR- = AVSS */
+#define SREF_VREF_AVSS SREF_1 /* VR+ = VREF+ and VR- = AVSS */
+#define SREF_VEREF_AVSS SREF_2 /* VR+ = VEREF+ and VR- = AVSS */
+//~ #define SREF_VEREF_AVSS SREF_3 /* VR+ = VEREF+ and VR- = AVSS */
+#define SREF_AVCC_VEREF SREF_4 /* VR+ = AVCC and VR- = VREF-/VEREF- */
+#define SREF_VREF_VEREF SREF_5 /* VR+ = VREF+ and VR- = VREF-/VEREF- */
+#define SREF_VEREF_VEREF SREF_6 /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
+//~ #define SREF_VEREF_VEREF SREF_7 /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
+
+#define ADC10SSEL_ADC10OSC ADC10SSEL_0 /* ADC10OSC */
+#define ADC10SSEL_ACLK ADC10SSEL_1 /* ACLK */
+#define ADC10SSEL_MCLK ADC10SSEL_2 /* MCLK */
+#define ADC10SSEL_SMCLK ADC10SSEL_3 /* SMCLK */
+
+#define INCH_A0 INCH_0 /* A0 */
+#define INCH_A1 INCH_1 /* A1 */
+#define INCH_A2 INCH_2 /* A2 */
+#define INCH_A3 INCH_3 /* A3 */
+#define INCH_A4 INCH_4 /* A4 */
+#define INCH_A5 INCH_5 /* A5 */
+#define INCH_A6 INCH_6 /* A6 */
+#define INCH_A7 INCH_7 /* A7 */
+#define INCH_VEREF_PLUS INCH_8 /* VeREF+ */
+#define INCH_VEREF_MINUS INCH_9 /* VREF-/VeREF- */
+#define INCH_TEMP INCH_10 /* Temperature sensor */
+#define INCH_VCC2 INCH_11 /* (VCC - VSS) / 2 */
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_adc12_h
+#define __msp430_headers_adc12_h
+
+/* adc12.h
+ *
+ * mspgcc project: MSP430 device headers
+ * ADC12 module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: adc12.h,v 1.11 2008/10/09 15:00:14 sb-sf Exp $
+ */
+
+/* Switches: none */
+
+#define ADC12CTL0_ 0x01A0 /* ADC12 Control 0 */
+sfrw(ADC12CTL0,ADC12CTL0_);
+#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */
+sfrw(ADC12CTL1,ADC12CTL1_);
+#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */
+sfrw(ADC12IFG,ADC12IFG_);
+#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */
+sfrw(ADC12IE,ADC12IE_);
+#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */
+sfrw(ADC12IV,ADC12IV_);
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+typedef struct {
+ volatile unsigned
+ adc12sc:1,
+ enc:1,
+ adc12tovie:1,
+ adc12ovie:1,
+ adc12on:1,
+ refon:1,
+ r2_5v:1,
+ msc:1,
+ sht0:4,
+ sht1:4;
+} __attribute__ ((packed)) adc12ctl0_t;
+
+typedef struct {
+ volatile unsigned
+ adc12busy:1,
+ conseq:2,
+ adc12ssel:2,
+ adc12div:3,
+ issh:1,
+ shp:1,
+ shs:2,
+ cstartadd:4;
+} __attribute__ ((packed)) adc12ctl1_t;
+
+typedef struct {
+ volatile unsigned
+ bit0:1,
+ bit1:1,
+ bit2:1,
+ bit3:1,
+ bit4:1,
+ bit5:1,
+ bit6:1,
+ bit7:1,
+ bit8:1,
+ bit9:1,
+ bit10:1,
+ bit11:1,
+ bit12:1,
+ bit13:1,
+ bit14:1,
+ bit15:1;
+} __attribute__ ((packed)) adc12xflg_t;
+
+/* The adc12 declaration itself */
+struct adc12_t {
+ adc12ctl0_t ctl0;
+ adc12ctl1_t ctl1;
+ adc12xflg_t ifg;
+ adc12xflg_t ie;
+ adc12xflg_t iv;
+};
+
+#ifdef __cplusplus
+extern "C" struct adc12_t adc12 asm("0x01A0");
+#else //__cplusplus
+struct adc12_t adc12 asm("0x01A0");
+#endif //__cplusplus
+
+#endif
+
+#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */
+#ifdef __ASSEMBLER__
+#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */
+#else
+#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
+#endif
+#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */
+sfrw(ADC12MEM0,ADC12MEM0_);
+#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */
+sfrw(ADC12MEM1,ADC12MEM1_);
+#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */
+sfrw(ADC12MEM2,ADC12MEM2_);
+#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */
+sfrw(ADC12MEM3,ADC12MEM3_);
+#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */
+sfrw(ADC12MEM4,ADC12MEM4_);
+#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */
+sfrw(ADC12MEM5,ADC12MEM5_);
+#define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */
+sfrw(ADC12MEM6,ADC12MEM6_);
+#define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */
+sfrw(ADC12MEM7,ADC12MEM7_);
+#define ADC12MEM8_ 0x0150 /* ADC12 Conversion Memory 8 */
+sfrw(ADC12MEM8,ADC12MEM8_);
+#define ADC12MEM9_ 0x0152 /* ADC12 Conversion Memory 9 */
+sfrw(ADC12MEM9,ADC12MEM9_);
+#define ADC12MEM10_ 0x0154 /* ADC12 Conversion Memory 10 */
+sfrw(ADC12MEM10,ADC12MEM10_);
+#define ADC12MEM11_ 0x0156 /* ADC12 Conversion Memory 11 */
+sfrw(ADC12MEM11,ADC12MEM11_);
+#define ADC12MEM12_ 0x0158 /* ADC12 Conversion Memory 12 */
+sfrw(ADC12MEM12,ADC12MEM12_);
+#define ADC12MEM13_ 0x015A /* ADC12 Conversion Memory 13 */
+sfrw(ADC12MEM13,ADC12MEM13_);
+#define ADC12MEM14_ 0x015C /* ADC12 Conversion Memory 14 */
+sfrw(ADC12MEM14,ADC12MEM14_);
+#define ADC12MEM15_ 0x015E /* ADC12 Conversion Memory 15 */
+sfrw(ADC12MEM15,ADC12MEM15_);
+
+#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */
+#ifdef __ASSEMBLER__
+#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */
+#else
+#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
+#endif
+#define ADC12MCTL0_ ADC12MCTL_ /* ADC12 Memory Control 0 */
+sfrb(ADC12MCTL0,ADC12MCTL0_);
+#define ADC12MCTL1_ 0x0081 /* ADC12 Memory Control 1 */
+sfrb(ADC12MCTL1,ADC12MCTL1_);
+#define ADC12MCTL2_ 0x0082 /* ADC12 Memory Control 2 */
+sfrb(ADC12MCTL2,ADC12MCTL2_);
+#define ADC12MCTL3_ 0x0083 /* ADC12 Memory Control 3 */
+sfrb(ADC12MCTL3,ADC12MCTL3_);
+#define ADC12MCTL4_ 0x0084 /* ADC12 Memory Control 4 */
+sfrb(ADC12MCTL4,ADC12MCTL4_);
+#define ADC12MCTL5_ 0x0085 /* ADC12 Memory Control 5 */
+sfrb(ADC12MCTL5,ADC12MCTL5_);
+#define ADC12MCTL6_ 0x0086 /* ADC12 Memory Control 6 */
+sfrb(ADC12MCTL6,ADC12MCTL6_);
+#define ADC12MCTL7_ 0x0087 /* ADC12 Memory Control 7 */
+sfrb(ADC12MCTL7,ADC12MCTL7_);
+#define ADC12MCTL8_ 0x0088 /* ADC12 Memory Control 8 */
+sfrb(ADC12MCTL8,ADC12MCTL8_);
+#define ADC12MCTL9_ 0x0089 /* ADC12 Memory Control 9 */
+sfrb(ADC12MCTL9,ADC12MCTL9_);
+#define ADC12MCTL10_ 0x008A /* ADC12 Memory Control 10 */
+sfrb(ADC12MCTL10,ADC12MCTL10_);
+#define ADC12MCTL11_ 0x008B /* ADC12 Memory Control 11 */
+sfrb(ADC12MCTL11,ADC12MCTL11_);
+#define ADC12MCTL12_ 0x008C /* ADC12 Memory Control 12 */
+sfrb(ADC12MCTL12,ADC12MCTL12_);
+#define ADC12MCTL13_ 0x008D /* ADC12 Memory Control 13 */
+sfrb(ADC12MCTL13,ADC12MCTL13_);
+#define ADC12MCTL14_ 0x008E /* ADC12 Memory Control 14 */
+sfrb(ADC12MCTL14,ADC12MCTL14_);
+#define ADC12MCTL15_ 0x008F /* ADC12 Memory Control 15 */
+sfrb(ADC12MCTL15,ADC12MCTL15_);
+
+/* ADC12CTL0 */
+#define ADC12SC 0x0001 /* ADC12 Start Conversion */
+#define ENC 0x0002 /* ADC12 Enable Conversion */
+#define ADC12TOVIE 0x0004 /* ADC12 Timer Overflow interrupt enable */
+#define ADC12OVIE 0x0008 /* ADC12 Overflow interrupt enable */
+#define ADC12ON 0x0010 /* ADC12 On/enable */
+#define REFON 0x0020 /* ADC12 Reference on */
+#define REF2_5V 0x0040 /* ADC12 Ref 0:1.5V / 1:2.5V */
+#define MSC 0x0080 /* ADC12 Multiple Sample Conversion */
+#define MSH 0x0080
+#define SHT00 0x0100 /* ADC12 Sample Hold 0 Select 0 */
+#define SHT01 0x0200 /* ADC12 Sample Hold 0 Select 1 */
+#define SHT02 0x0400 /* ADC12 Sample Hold 0 Select 2 */
+#define SHT03 0x0800 /* ADC12 Sample Hold 0 Select 3 */
+#define SHT10 0x1000 /* ADC12 Sample Hold 0 Select 0 */
+#define SHT11 0x2000 /* ADC12 Sample Hold 1 Select 1 */
+#define SHT12 0x4000 /* ADC12 Sample Hold 2 Select 2 */
+#define SHT13 0x8000 /* ADC12 Sample Hold 3 Select 3 */
+
+#define SHT0_0 (0<<8) /* 4 */
+#define SHT0_1 (1<<8) /* 8 */
+#define SHT0_2 (2<<8) /* 16 */
+#define SHT0_3 (3<<8) /* 32 */
+#define SHT0_4 (4<<8) /* 64 */
+#define SHT0_5 (5<<8) /* 96 */
+#define SHT0_6 (6<<8) /* 128 */
+#define SHT0_7 (7<<8) /* 192 */
+#define SHT0_8 (8<<8) /* 256 */
+#define SHT0_9 (9<<8) /* 384 */
+#define SHT0_10 (10<<8) /* 512 */
+#define SHT0_11 (11<<8) /* 768 */
+#define SHT0_12 (12<<8) /* 1024 */
+#define SHT0_13 (13<<8) /* 1024 */
+#define SHT0_14 (14<<8) /* 1024 */
+#define SHT0_15 (15<<8) /* 1024 */
+
+#define SHT1_0 (0<<12) /* 4 */
+#define SHT1_1 (1<<12) /* 8 */
+#define SHT1_2 (2<<12) /* 16 */
+#define SHT1_3 (3<<12) /* 32 */
+#define SHT1_4 (4<<12) /* 64 */
+#define SHT1_5 (5<<12) /* 96 */
+#define SHT1_6 (6<<12) /* 128 */
+#define SHT1_7 (7<<12) /* 192 */
+#define SHT1_8 (8<<12) /* 256 */
+#define SHT1_9 (9<<12) /* 384 */
+#define SHT1_10 (10<<12) /* 512 */
+#define SHT1_11 (11<<12) /* 768 */
+#define SHT1_12 (12<<12) /* 1024 */
+#define SHT1_13 (13<<12) /* 1024 */
+#define SHT1_14 (14<<12) /* 1024 */
+#define SHT1_15 (15<<12) /* 1024 */
+
+/* ADC12CTL1 */
+#define ADC12BUSY 0x0001 /* ADC12 Busy */
+#define CONSEQ0 0x0002 /* ADC12 Conversion Sequence Select 0 */
+#define CONSEQ1 0x0004 /* ADC12 Conversion Sequence Select 1 */
+#define ADC12SSEL0 0x0008 /* ADC12 Clock Source Select 0 */
+#define ADC12SSEL1 0x0010 /* ADC12 Clock Source Select 1 */
+#define ADC12DIV0 0x0020 /* ADC12 Clock Divider Select 0 */
+#define ADC12DIV1 0x0040 /* ADC12 Clock Divider Select 1 */
+#define ADC12DIV2 0x0080 /* ADC12 Clock Divider Select 2 */
+#define ISSH 0x0100 /* ADC12 Invert Sample Hold Signal */
+#define SHP 0x0200 /* ADC12 Sample/Hold Pulse Mode */
+#define SHS0 0x0400 /* ADC12 Sample/Hold Source 0 */
+#define SHS1 0x0800 /* ADC12 Sample/Hold Source 1 */
+#define CSTARTADD0 0x1000 /* ADC12 Conversion Start Address 0 */
+#define CSTARTADD1 0x2000 /* ADC12 Conversion Start Address 1 */
+#define CSTARTADD2 0x4000 /* ADC12 Conversion Start Address 2 */
+#define CSTARTADD3 0x8000 /* ADC12 Conversion Start Address 3 */
+
+#define CONSEQ_0 (0<<1) /* Single-channel, single-conversion */
+#define CONSEQ_1 (1<<1) /* Sequence-of-channels */
+#define CONSEQ_2 (2<<1) /* Repeat-single-channel */
+#define CONSEQ_3 (3<<1) /* Repeat-sequence-of-channels */
+#define ADC12SSEL_0 (0<<3) /* ADC12OSC */
+#define ADC12SSEL_1 (1<<3) /* ACLK */
+#define ADC12SSEL_2 (2<<3) /* MCLK */
+#define ADC12SSEL_3 (3<<3) /* SMCLK */
+#define ADC12DIV_0 (0<<5)
+#define ADC12DIV_1 (1<<5)
+#define ADC12DIV_2 (2<<5)
+#define ADC12DIV_3 (3<<5)
+#define ADC12DIV_4 (4<<5)
+#define ADC12DIV_5 (5<<5)
+#define ADC12DIV_6 (6<<5)
+#define ADC12DIV_7 (7<<5)
+#define SHS_0 (0<<10) /* ADC12SC bit */
+#define SHS_1 (1<<10) /* Timer_A.OUT1 */
+#define SHS_2 (2<<10) /* Timer_B.OUT0 */
+#define SHS_3 (3<<10) /* Timer_B.OUT1 */
+#define CSTARTADD_0 (0<<12)
+#define CSTARTADD_1 (1<<12)
+#define CSTARTADD_2 (2<<12)
+#define CSTARTADD_3 (3<<12)
+#define CSTARTADD_4 (4<<12)
+#define CSTARTADD_5 (5<<12)
+#define CSTARTADD_6 (6<<12)
+#define CSTARTADD_7 (7<<12)
+#define CSTARTADD_8 (8<<12)
+#define CSTARTADD_9 (9<<12)
+#define CSTARTADD_10 (10<<12)
+#define CSTARTADD_11 (11<<12)
+#define CSTARTADD_12 (12<<12)
+#define CSTARTADD_13 (13<<12)
+#define CSTARTADD_14 (14<<12)
+#define CSTARTADD_15 (15<<12)
+
+/* ADC12MCTLx */
+#define INCH_0 0 /* A0 */
+#define INCH_1 1 /* A1 */
+#define INCH_2 2 /* A2 */
+#define INCH_3 3 /* A3 */
+#define INCH_4 4 /* A4 */
+#define INCH_5 5 /* A5 */
+#define INCH_6 6 /* A6 */
+#define INCH_7 7 /* A7 */
+#define INCH_8 8 /* VeREF+ */
+#define INCH_9 9 /* VREF\96/VeREF\96 */
+#define INCH_10 10 /* Temperature diode */
+#define INCH_11 11 /* (AVCC \96 AVSS) / 2 */
+#define INCH_12 12 /* (AVCC \96 AVSS) / 2 */
+#define INCH_13 13 /* (AVCC \96 AVSS) / 2 */
+#define INCH_14 14 /* (AVCC \96 AVSS) / 2 */
+#define INCH_15 15 /* (AVCC \96 AVSS) / 2 */
+
+#define SREF_0 (0<<4) /* VR+ = AVCC and VR\96 = AVSS */
+#define SREF_1 (1<<4) /* VR+ = VREF+ and VR\96 = AVSS */
+#define SREF_2 (2<<4) /* VR+ = VeREF+ and VR\96 = AVSS */
+#define SREF_3 (3<<4) /* VR+ = VeREF+ and VR\96 = AVSS */
+#define SREF_4 (4<<4) /* VR+ = AVCC and VR\96 = VREF\96/ VeREF\96 */
+#define SREF_5 (5<<4) /* VR+ = VREF+ and VR\96 = VREF\96/ VeREF\96 */
+#define SREF_6 (6<<4) /* VR+ = VeREF+ and VR\96 = VREF\96/ VeREF\96 */
+#define SREF_7 (7<<4) /* VR+ = VeREF+ and VR\96 = VREF\96/ VeREF\96 */
+#define EOS 0x80
+
+/* Aliases by mspgcc */
+#define SHT0_DIV4 SHT0_0 /* 4 */
+#define SHT0_DIV8 SHT0_1 /* 8 */
+#define SHT0_DIV16 SHT0_2 /* 16 */
+#define SHT0_DIV32 SHT0_3 /* 32 */
+#define SHT0_DIV64 SHT0_4 /* 64 */
+#define SHT0_DIV96 SHT0_5 /* 96 */
+#define SHT0_DIV128 SHT0_6 /* 128 */
+#define SHT0_DIV192 SHT0_7 /* 192 */
+#define SHT0_DIV256 SHT0_8 /* 256 */
+#define SHT0_DIV384 SHT0_9 /* 384 */
+#define SHT0_DIV512 SHT0_10 /* 512 */
+#define SHT0_DIV768 SHT0_11 /* 768 */
+#define SHT0_DIV1024 SHT0_12 /* 1024 */
+
+#define SHT1_DIV4 SHT1_0 /* 4 */
+#define SHT1_DIV8 SHT1_1 /* 8 */
+#define SHT1_DIV16 SHT1_2 /* 16 */
+#define SHT1_DIV32 SHT1_3 /* 32 */
+#define SHT1_DIV64 SHT1_4 /* 64 */
+#define SHT1_DIV96 SHT1_5 /* 96 */
+#define SHT1_DIV128 SHT1_6 /* 128 */
+#define SHT1_DIV192 SHT1_7 /* 192 */
+#define SHT1_DIV256 SHT1_8 /* 256 */
+#define SHT1_DIV384 SHT1_9 /* 384 */
+#define SHT1_DIV512 SHT1_10 /* 512 */
+#define SHT1_DIV768 SHT1_11 /* 768 */
+#define SHT1_DIV1024 SHT1_12 /* 1024 */
+
+#define CONSEQ_SINGLE CONSEQ_0 /* Single-channel, single-conversion */
+#define CONSEQ_SEQUENCE CONSEQ_1 /* Sequence-of-channels */
+#define CONSEQ_REPEAT_SINGLE CONSEQ_2 /* Repeat-single-channel */
+#define CONSEQ_REPEAT_SEQUENCE CONSEQ_3 /* Repeat-sequence-of-channels */
+#define ADC12SSEL_ADC12OSC ADC12SSEL_0 /* ADC12OSC */
+#define ADC12SSEL_ACLK ADC12SSEL_1 /* ACLK */
+#define ADC12SSEL_MCLK ADC12SSEL_2 /* MCLK */
+#define ADC12SSEL_SMCLK ADC12SSEL_3 /* SMCLK */
+#define SHS_ADC12SC SHS_0 /* ADC12SC bit */
+#define SHS_TACCR1 SHS_1 /* Timer_A.OUT1 */
+#define SHS_TBCCR0 SHS_2 /* Timer_B.OUT0 */
+#define SHS_TBCCR1 SHS_3 /* Timer_B.OUT1 */
+
+#define INCH_A0 0 /* A0 */
+#define INCH_A1 1 /* A1 */
+#define INCH_A2 2 /* A2 */
+#define INCH_A3 3 /* A3 */
+#define INCH_A4 4 /* A4 */
+#define INCH_A5 5 /* A5 */
+#define INCH_A6 6 /* A6 */
+#define INCH_A7 7 /* A7 */
+#define INCH_VEREF_PLUS 8 /* VeREF+ */
+#define INCH_VEREF_MINUS 9 /* VREF\96/VeREF\96 */
+#define INCH_TEMP 10 /* Temperature diode */
+#define INCH_VCC2 11 /* (AVCC \96 AVSS) / 2 */
+
+
+#define SREF_AVCC_AVSS SREF_0 /* VR+ = AVCC and VR\96 = AVSS */
+#define SREF_VREF_AVSS SREF_1 /* VR+ = VREF+ and VR\96 = AVSS */
+#define SREF_VEREF_AVSS SREF_2 /* VR+ = VeREF+ and VR\96 = AVSS */
+//~ #define SREF_VEREF_AVSS SREF_3 /* VR+ = VeREF+ and VR\96 = AVSS */
+#define SREF_AVCC_VEREF SREF_4 /* VR+ = AVCC and VR\96 = VREF\96/ VeREF\96 */
+#define SREF_VREF_VEREF SREF_5 /* VR+ = VREF+ and VR\96 = VREF\96/ VeREF\96 */
+#define SREF_VEREF_VEREF SREF_6 /* VR+ = VeREF+ and VR\96 = VREF\96/ VeREF\96 */
+//~ #define SREF_VEREF_VEREF SREF_7 /* VR+ = VeREF+ and VR\96 = VREF\96/ VeREF\96 */
+
+#endif
+
--- /dev/null
+#ifndef __msp430_headers_clock_h
+#define __msp430_headers_clock_h
+
+/* basic_clock.h
+ *
+ * mspgcc project: MSP430 device headers
+ * BASIC_CLOCK module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: basic_clock.h,v 1.7 2007/07/20 12:59:02 coppice Exp $
+ */
+
+/* Switches:
+__MSP430_HAS_BC2__
+*/
+
+#define DCOCTL_ 0x0056 /* DCO Clock Frequency Control */
+sfrb(DCOCTL,DCOCTL_);
+#define BCSCTL1_ 0x0057 /* Basic Clock System Control 1 */
+sfrb(BCSCTL1,BCSCTL1_);
+#define BCSCTL2_ 0x0058 /* Basic Clock System Control 2 */
+sfrb(BCSCTL2,BCSCTL2_);
+#if defined(__MSP430_HAS_BC2__)
+#define BCSCTL3_ 0x0053 /* Basic Clock System Control 3 */
+sfrb(BCSCTL3, BCSCTL3_);
+#endif
+
+#define MOD0 0x01 /* Modulation Bit 0 */
+#define MOD1 0x02 /* Modulation Bit 1 */
+#define MOD2 0x04 /* Modulation Bit 2 */
+#define MOD3 0x08 /* Modulation Bit 3 */
+#define MOD4 0x10 /* Modulation Bit 4 */
+#define DCO0 0x20 /* DCO Select Bit 0 */
+#define DCO1 0x40 /* DCO Select Bit 1 */
+#define DCO2 0x80 /* DCO Select Bit 2 */
+
+#define RSEL0 0x01 /* Resistor Select Bit 0 */
+#define RSEL1 0x02 /* Resistor Select Bit 1 */
+#define RSEL2 0x04 /* Resistor Select Bit 2 */
+#if defined(__MSP430_HAS_BC2__)
+#define RSEL3 0x08 /* Resistor Select Bit 3 */
+#else
+#define XT5V 0x08 /* XT5V should always be reset */
+#endif
+#define DIVA0 0x10 /* ACLK Divider 0 */
+#define DIVA1 0x20 /* ACLK Divider 1 */
+#define XTS 0x40 /* LFXTCLK 0:Low Freq. / 1: High Freq. */
+#define XT2OFF 0x80 /* Enable XT2CLK */
+
+#define DIVA_0 (0<<4) /* ACLK Divider 0: /1 */
+#define DIVA_1 (1<<4) /* ACLK Divider 1: /2 */
+#define DIVA_2 (2<<4) /* ACLK Divider 2: /4 */
+#define DIVA_3 (3<<4) /* ACLK Divider 3: /8 */
+
+#if !defined(__MSP430_HAS_BC2__)
+#define DCOR 0x01 /* Enable External Resistor : 1 */
+#endif
+#define DIVS0 0x02 /* SMCLK Divider 0 */
+#define DIVS1 0x04 /* SMCLK Divider 1 */
+#define SELS 0x08 /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
+#define DIVM0 0x10 /* MCLK Divider 0 */
+#define DIVM1 0x20 /* MCLK Divider 1 */
+#define SELM0 0x40 /* MCLK Source Select 0 */
+#define SELM1 0x80 /* MCLK Source Select 1 */
+
+#define DIVS_0 (0<<1) /* SMCLK Divider 0: /1 */
+#define DIVS_1 (1<<1) /* SMCLK Divider 1: /2 */
+#define DIVS_2 (2<<1) /* SMCLK Divider 2: /4 */
+#define DIVS_3 (3<<1) /* SMCLK Divider 3: /8 */
+
+#define DIVM_0 (0<<4) /* MCLK Divider 0: /1 */
+#define DIVM_1 (1<<4) /* MCLK Divider 1: /2 */
+#define DIVM_2 (2<<4) /* MCLK Divider 2: /4 */
+#define DIVM_3 (3<<4) /* MCLK Divider 3: /8 */
+
+#define SELM_0 (0<<6) /* MCLK Source Select 0: DCOCLK */
+#define SELM_1 (1<<6) /* MCLK Source Select 1: DCOCLK */
+#define SELM_2 (2<<6) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
+#define SELM_3 (3<<6) /* MCLK Source Select 3: LFXTCLK */
+
+#if defined(__MSP430_HAS_BC2__)
+#define LFXT1OF 0x01 /* Low/high Frequency Oscillator Fault Flag */
+#define XT2OF 0x02 /* High frequency oscillator 2 fault flag */
+#define XCAP0 0x04 /* XIN/XOUT Cap 0 */
+#define XCAP1 0x08 /* XIN/XOUT Cap 1 */
+#define LFXT1S0 0x10 /* Mode 0 for LFXT1 (XTS = 0) */
+#define LFXT1S1 0x20 /* Mode 1 for LFXT1 (XTS = 0) */
+#define XT2S0 0x40 /* Mode 0 for XT2 */
+#define XT2S1 0x80 /* Mode 1 for XT2 */
+
+#define XCAP_0 (0<<2) /* XIN/XOUT Cap : 0 pF */
+#define XCAP_1 (1<<2) /* XIN/XOUT Cap : 6 pF */
+#define XCAP_2 (2<<2) /* XIN/XOUT Cap : 10 pF */
+#define XCAP_3 (3<<2) /* XIN/XOUT Cap : 12.5 pF */
+
+#define LFXT1S_0 (0<<4) /* Mode 0 for LFXT1 : Normal operation */
+#define LFXT1S_1 (1<<4) /* Mode 1 for LFXT1 : Bypass amplitude regulation */
+#define LFXT1S_2 (2<<4) /* Mode 2 for LFXT1 : Reserved */
+#define LFXT1S_3 (3<<4) /* Mode 3 for LFXT1 : Digital input signal */
+
+#define XT2S_0 (0<<6) /* Mode 0 for XT2 : 0.4 - 1 MHz */
+#define XT2S_1 (1<<6) /* Mode 1 for XT2 : 1 - 4 MHz */
+#define XT2S_2 (2<<6) /* Mode 2 for XT2 : 2 - 16 MHz */
+#define XT2S_3 (3<<6) /* Mode 3 for XT2 : Digital input signal */
+#endif
+
+/* Aliases by mspgcc */
+#define DIVA_DIV1 DIVA_0
+#define DIVA_DIV2 DIVA_1
+#define DIVA_DIV4 DIVA_2
+#define DIVA_DIV8 DIVA_3
+
+#define DIVS_DIV1 DIVS_0
+#define DIVS_DIV2 DIVS_1
+#define DIVS_DIV4 DIVS_2
+#define DIVS_DIV8 DIVS_3
+
+#define DIVM_DIV1 DIVM_0
+#define DIVM_DIV2 DIVM_1
+#define DIVM_DIV4 DIVM_2
+#define DIVM_DIV8 DIVM_3
+
+#define SELM_DCOCLK SELM_0
+/*#define SELM_DCOCLK SELM_1*/
+#define SELM_XT2CLK SELM_2
+#define SELM_LFXTCLK SELM_3
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_basic_timer_h
+#define __msp430_headers_basic_timer_h
+
+/* basic_timer.h
+ *
+ * mspgcc project: MSP430 device headers
+ * BASIC_TIMER module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: basic_timer.h,v 1.5 2006/06/07 13:01:30 coppice Exp $
+ */
+
+/* Switches:
+__MSP430_HAS_BT_RTC__ - if device has the enhanced BT with RTC
+
+*/
+
+#define BTCTL_ 0x0040 /* Basic Timer Control */
+sfrb(BTCTL, BTCTL_);
+
+/* The bit names have been prefixed with "BT" */
+#define BTIP0 0x01
+#define BTIP1 0x02
+#define BTIP2 0x04
+#define BTFRFQ0 0x08
+#define BTFRFQ1 0x10
+#define BTDIV 0x20 /* fCLK2 = ACLK:256 */
+#define BTRESET 0x40 /* BT is reset and BTIFG is reset if this bit is set */
+#define BTHOLD 0x40 /* BT1 is held if this bit is set */
+#define BTSSEL 0x80 /* fBT = fMCLK (main clock) */
+
+#define BTCNT1_ 0x0046 /* Basic Timer Count 1 */
+sfrb(BTCNT1, BTCNT1_);
+#define BTCNT2_ 0x0047 /* Basic Timer Count 2 */
+sfrb(BTCNT2, BTCNT2_);
+
+/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
+#define BT_fCLK2_ACLK 0x00
+#define BT_fCLK2_ACLK_DIV256 BTDIV
+#define BT_fCLK2_MCLK BTSSEL
+
+/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
+#define BT_fCLK2_DIV2 0 /* fINT = fCLK2:2 (default) */
+#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
+#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
+#define BT_fCLK2_DIV16 (BTIP1|BTIP0) /* fINT = fCLK2:16 */
+#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
+#define BT_fCLK2_DIV64 (BTIP2|BTIP0) /* fINT = fCLK2:64 */
+#define BT_fCLK2_DIV128 (BTIP2|BTIP1) /* fINT = fCLK2:128 */
+#define BT_fCLK2_DIV256 (BTIP2|BTIP1|BTIP0) /* fINT = fCLK2:256 */
+/* Frequency of LCD coded with Bits 3-4 */
+#define BT_fLCD_DIV32 0 /* fLCD = fACLK:32 (default) */
+#define BT_fLCD_DIV64 (BTFRFQ0) /* fLCD = fACLK:64 */
+#define BT_fLCD_DIV128 (BTFRFQ1) /* fLCD = fACLK:128 */
+#define BT_fLCD_DIV256 (BTFRFQ1|BTFRFQ0) /* fLCD = fACLK:256 */
+/* LCD frequency values with fBT=fACLK */
+#define BT_fLCD_1K 0 /* fACLK:32 (default) */
+#define BT_fLCD_512 (BTFRFQ0) /* fACLK:64 */
+#define BT_fLCD_256 (BTFRFQ1) /* fACLK:128 */
+#define BT_fLCD_128 (BTFRFQ1|BTFRFQ0) /* fACLK:256 */
+/* LCD frequency values with fBT=fMCLK */
+#define BT_fLCD_31K (BTSSEL) /* fMCLK:32 */
+#define BT_fLCD_15_5K (BTSSEL|BTFRFQ0) /* fMCLK:64 */
+#define BT_fLCD_7_8K (BTSSEL|BTFRFQ1|BTFRFQ0) /* fMCLK:256 */
+/* With assumed values of fACLK=32KHz, fMCLK=1MHz */
+/* fBT=fACLK is thought for longer interval times */
+#define BT_ADLY_0_064 0 /* 0.064ms interval (default) */
+#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
+#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
+#define BT_ADLY_0_5 (BTIP1|BTIP0) /* 0.5ms " */
+#define BT_ADLY_1 (BTIP2) /* 1ms " */
+#define BT_ADLY_2 (BTIP2|BTIP0) /* 2ms " */
+#define BT_ADLY_4 (BTIP2|BTIP1) /* 4ms " */
+#define BT_ADLY_8 (BTIP2|BTIP1|BTIP0) /* 8ms " */
+#define BT_ADLY_16 (BTDIV) /* 16ms " */
+#define BT_ADLY_32 (BTDIV|BTIP0) /* 32ms " */
+#define BT_ADLY_64 (BTDIV|BTIP1) /* 64ms " */
+#define BT_ADLY_125 (BTDIV|BTIP1|BTIP0) /* 125ms " */
+#define BT_ADLY_250 (BTDIV|BTIP2) /* 250ms " */
+#define BT_ADLY_500 (BTDIV|BTIP2|BTIP0) /* 500ms " */
+#define BT_ADLY_1000 (BTDIV|BTIP2|BTIP1) /* 1000ms " */
+#define BT_ADLY_2000 (BTDIV|BTIP2|BTIP1|BTIP0) /* 2000ms " */
+/* fCLK2=fMCLK (1MHz) is thought for short interval times */
+/* the timing for short intervals is more precise than ACLK */
+/* NOTE */
+/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
+/* Too low interval times result in too interrupts more frequent than the
+ processor can handle! */
+#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
+#define BT_MDLY_0_004 (BTSSEL|BTIP0) /* 0.004ms " *** too short for */
+#define BT_MDLY_0_008 (BTSSEL|BTIP1) /* 0.008ms " *** interrupt */
+#define BT_MDLY_0_016 (BTSSEL|BTIP1|BTIP0) /* 0.016ms " *** handling */
+#define BT_MDLY_0_032 (BTSSEL|BTIP2) /* 0.032ms " */
+#define BT_MDLY_0_064 (BTSSEL|BTIP2|BTIP0) /* 0.064ms " */
+#define BT_MDLY_0_125 (BTSSEL|BTIP2|BTIP1) /* 0.125ms " */
+#define BT_MDLY_0_25 (BTSSEL|BTIP2|BTIP1|BTIP0) /* 0.25ms " */
+
+/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
+/* this is for BT */
+#define BTRESET_CNT1 (BTRESET) /* BTCNT1 is reset while BTRESET is set */
+#define BTRESET_CNT1_2 (BTRESET|BTDIV) /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
+/* this is for BT1 */
+#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
+#define BTHOLD_CNT1_2 (BTHOLD|BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
+
+#if defined(__MSP430_HAS_BT_RTC__)
+
+#define RTCCTL_ 0x0041 /* Real Time Clock Control */
+sfrb(RTCCTL, RTCCTL_);
+#define RTCNT1_ 0x0042 /* Real Time Counter 1 */
+sfrb(RTCNT1, RTCNT1_);
+#define RTCNT2_ 0x0043 /* Real Time Counter 2 */
+sfrb(RTCNT2, RTCNT2_);
+#define RTCNT3_ 0x0044 /* Real Time Counter 3 */
+sfrb(RTCNT3, RTCNT3_);
+#define RTCNT4_ 0x0045 /* Real Time Counter 4 */
+sfrb(RTCNT4, RTCNT4_);
+#define RTCDAY_ 0x004C /* Real Time Clock Day */
+sfrb(RTCDAY, RTCDAY_);
+#define RTCMON_ 0x004D /* Real Time Clock Month */
+sfrb(RTCMON, RTCMON_);
+#define RTCYEARL_ 0x004E /* Real Time Clock Year (Low Byte) */
+sfrb(RTCYEARL, RTCYEARL_);
+#define RTCYEARH_ 0x004F /* Real Time Clock Year (High Byte) */
+sfrb(RTCYEARH, RTCYEARH_);
+
+#define RTCSEC RTCNT1
+#define RTCMIN RTCNT2
+#define RTCHOUR RTCNT3
+#define RTCDOW RTCNT4
+
+#define RTCTL_ 0x0040 /* Basic/Real Timer Control */
+sfrb(RTCTL, RTCTL_);
+
+#define RTCTIM0 RTCNT12
+#define RTCTIM1 RTCNT34
+
+#define RTCBCD (0x80) /* RTC BCD Select */
+#define RTCHOLD (0x40) /* RTC Hold */
+#define RTCMODE1 (0x20) /* RTC Mode 1 */
+#define RTCMODE0 (0x10) /* RTC Mode 0 */
+#define RTCTEV1 (0x08) /* RTC Time Event 1 */
+#define RTCTEV0 (0x04) /* RTC Time Event 0 */
+#define RTCIE (0x02) /* RTC Interrupt Enable */
+#define RTCFG (0x01) /* RTC Event Flag */
+
+#define RTCTEV_0 (0<<2) /* RTC Time Event: 0 */
+#define RTCTEV_1 (1<<2) /* RTC Time Event: 1 */
+#define RTCTEV_2 (2<<2) /* RTC Time Event: 2 */
+#define RTCTEV_3 (3<<2) /* RTC Time Event: 3 */
+#define RTCMODE_0 (0<<4) /* RTC Mode: 0 */
+#define RTCMODE_1 (1<<4) /* RTC Mode: 1 */
+#define RTCMODE_2 (2<<4) /* RTC Mode: 2 */
+#define RTCMODE_3 (3<<4) /* RTC Mode: 3 */
+
+#endif
+
+/* INTERRUPT CONTROL BITS */
+/* #define BTIE 0x80 */
+/* #define BTIFG 0x80 */
+/* #define BTME 0x80 */
+
+#endif
--- /dev/null
+
+#ifndef __msp430_headers_common_h
+#define __msp430_headers_common_h
+
+/* common.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Common register definitions
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: common.h,v 1.6 2008/10/09 15:00:14 sb-sf Exp $
+ */
+
+/* Switches: none */
+
+#define BIT0 0x0001
+#define BIT1 0x0002
+#define BIT2 0x0004
+#define BIT3 0x0008
+#define BIT4 0x0010
+#define BIT5 0x0020
+#define BIT6 0x0040
+#define BIT7 0x0080
+#define BIT8 0x0100
+#define BIT9 0x0200
+#define BITA 0x0400
+#define BITB 0x0800
+#define BITC 0x1000
+#define BITD 0x2000
+#define BITE 0x4000
+#define BITF 0x8000
+
+#define C 0x0001
+#define Z 0x0002
+#define N 0x0004
+#define V 0x0100
+#define GIE 0x0008
+#define CPUOFF 0x0010
+#define OSCOFF 0x0020
+#define SCG0 0x0040
+#define SCG1 0x0080
+
+#ifdef __ASSEMBLER__ /* Begin #defines for assembler */
+#define LPM0 CPUOFF
+#define LPM1 SCG0+CPUOFF
+#define LPM2 SCG1+CPUOFF
+#define LPM3 SCG1+SCG0+CPUOFF
+#define LPM4 SCG1+SCG0+OSCOFF+CPUOFF
+#else /* Begin #defines for C */
+#define LPM0_bits CPUOFF
+#define LPM1_bits SCG0+CPUOFF
+#define LPM2_bits SCG1+CPUOFF
+#define LPM3_bits SCG1+SCG0+CPUOFF
+#define LPM4_bits SCG1+SCG0+OSCOFF+CPUOFF
+
+#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
+#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
+#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
+#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
+#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
+#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
+#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
+#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
+#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
+#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
+#endif /* End #defines for C */
+
+#define WDTCTL_ 0x0120 /* Watchdog Timer Control */
+sfrw (WDTCTL,WDTCTL_);
+/* The bit names have been prefixed with "WDT" */
+#define WDTIS0 0x0001
+#define WDTIS1 0x0002
+#define WDTSSEL 0x0004
+#define WDTCNTCL 0x0008
+#define WDTTMSEL 0x0010
+#define WDTNMI 0x0020
+#define WDTNMIES 0x0040
+#define WDTHOLD 0x0080
+
+#define WDTPW 0x5A00
+
+/* WDT-interval times [1ms] coded with Bits 0-2 */
+/* WDT is clocked by fMCLK (assumed 1MHz) */
+#define WDT_MDLY_32 (WDTPW|WDTTMSEL|WDTCNTCL) /* 32ms interval (default) */
+#define WDT_MDLY_8 (WDTPW|WDTTMSEL|WDTCNTCL|WDTIS0) /* 8ms " */
+#define WDT_MDLY_0_5 (WDTPW|WDTTMSEL|WDTCNTCL|WDTIS1) /* 0.5ms " */
+#define WDT_MDLY_0_064 (WDTPW|WDTTMSEL|WDTCNTCL|WDTIS1|WDTIS0) /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ADLY_1000 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL) /* 1000ms " */
+#define WDT_ADLY_250 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL|WDTIS0) /* 250ms " */
+#define WDT_ADLY_16 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL|WDTIS1) /* 16ms " */
+#define WDT_ADLY_1_9 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL|WDTIS1|WDTIS0) /* 1.9ms " */
+/* Watchdog mode -> reset after expired time */
+/* WDT is clocked by fMCLK (assumed 1MHz) */
+#define WDT_MRST_32 (WDTPW|WDTCNTCL) /* 32ms interval (default) */
+#define WDT_MRST_8 (WDTPW|WDTCNTCL|WDTIS0) /* 8ms " */
+#define WDT_MRST_0_5 (WDTPW|WDTCNTCL|WDTIS1) /* 0.5ms " */
+#define WDT_MRST_0_064 (WDTPW|WDTCNTCL|WDTIS1|WDTIS0) /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ARST_1000 (WDTPW|WDTCNTCL|WDTSSEL) /* 1000ms " */
+#define WDT_ARST_250 (WDTPW|WDTCNTCL|WDTSSEL|WDTIS0) /* 250ms " */
+#define WDT_ARST_16 (WDTPW|WDTCNTCL|WDTSSEL|WDTIS1) /* 16ms " */
+#define WDT_ARST_1_9 (WDTPW|WDTCNTCL|WDTSSEL|WDTIS1|WDTIS0) /* 1.9ms " */
+
+/* INTERRUPT CONTROL */
+/* These two bits are defined in the Special Function Registers */
+/* #define WDTIE 0x01 */
+/* #define WDTIFG 0x01 */
+
+/* Aliases by mspgcc */
+#define WDTIS_0 0x0000
+#define WDTIS_1 0x0001
+#define WDTIS_2 0x0002
+#define WDTIS_3 0x0003
+
+
+/* Backwards compatibility to older versions of the header files.
+ Please consider using the new names.
+ */
+#ifdef __MSP430_HAS_PORT1__
+ #define __msp430_have_port1
+#endif
+
+#ifdef __MSP430_HAS_PORT2__
+ #define __msp430_have_port2
+#endif
+
+#ifdef __MSP430_HAS_PORT3__
+ #define __msp430_have_port3
+#endif
+
+#ifdef __MSP430_HAS_PORT4__
+ #define __msp430_have_port4
+#endif
+
+#ifdef __MSP430_HAS_PORT5__
+ #define __msp430_have_port5
+#endif
+
+#ifdef __MSP430_HAS_PORT6__
+ #define __msp430_have_port6
+#endif
+
+#ifdef __MSP430_HAS_UART1__
+ #define __msp430_have_usart1
+#endif
+
+#ifdef __MSP430_HAS_TB7__
+ #define __msp430_have_timerb7
+#endif
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_compa_h
+#define __msp430_headers_compa_h
+
+/* compa.h
+ *
+ * mspgcc project: MSP430 device headers
+ * COMPA module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: compa.h,v 1.6 2005/08/17 14:28:46 coppice Exp $
+ */
+
+/* Switches:
+__MSP430_HAS_CAPLUS__
+*/
+
+#define CACTL1_ 0x0059 /* Comparator A Control 1 */
+sfrb(CACTL1,CACTL1_);
+#define CACTL2_ 0x005A /* Comparator A Control 2 */
+sfrb(CACTL2,CACTL2_);
+#define CAPD_ 0x005B /* Comparator A Port Disable */
+sfrb(CAPD,CAPD_);
+
+#define CAIFG 0x01 /* Comp. A Interrupt Flag */
+#define CAIE 0x02 /* Comp. A Interrupt Enable */
+#define CAIES 0x04 /* Comp. A Int. Edge Select: 0:rising / 1:falling */
+#define CAON 0x08 /* Comp. A enable */
+#define CAREF0 0x10 /* Comp. A Internal Reference Select 0 */
+#define CAREF1 0x20 /* Comp. A Internal Reference Select 1 */
+#define CARSEL 0x40 /* Comp. A Internal Reference Enable */
+#define CAEX 0x80 /* Comp. A Exchange Inputs */
+
+#define CAREF_0 0x00 /* Comp. A Int. Ref. Select 0 : Off */
+#define CAREF_1 0x10 /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
+#define CAREF_2 0x20 /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
+#define CAREF_3 0x30 /* Comp. A Int. Ref. Select 3 : Vt*/
+
+#define CAOUT 0x01 /* Comp. A Output */
+#define CAF 0x02 /* Comp. A Enable Output Filter */
+#define P2CA0 0x04 /* Comp. A Connect External Signal to CA0 : 1 */
+#define P2CA1 0x08 /* Comp. A Connect External Signal to CA1 : 1 */
+#if defined(__MSP430_HAS_CAPLUS__)
+#define P2CA2 0x10 /* Comp. A -Terminal Multiplexer */
+#define P2CA3 0x20 /* Comp. A -Terminal Multiplexer */
+#define P2CA4 0x40 /* Comp. A +Terminal Multiplexer */
+#define CASHORT 0x80 /* Comp. A Short + and - Terminals */
+#else
+#define CACTL24 0x10
+#define CACTL25 0x20
+#define CACTL26 0x40
+#define CACTL27 0x80
+#endif
+
+#define CAPD0 0x01 /* Comp. A Disable Input Buffer of Port Register .0 */
+#define CAPD1 0x02 /* Comp. A Disable Input Buffer of Port Register .1 */
+#define CAPD2 0x04 /* Comp. A Disable Input Buffer of Port Register .2 */
+#define CAPD3 0x08 /* Comp. A Disable Input Buffer of Port Register .3 */
+#define CAPD4 0x10 /* Comp. A Disable Input Buffer of Port Register .4 */
+#define CAPD5 0x20 /* Comp. A Disable Input Buffer of Port Register .5 */
+#define CAPD6 0x40 /* Comp. A Disable Input Buffer of Port Register .6 */
+#define CAPD7 0x80 /* Comp. A Disable Input Buffer of Port Register .7 */
+
+/* Aliases by mspgcc */
+#define CAREF_OFF CAREF_0
+#define CAREF_025 CAREF_1
+#define CAREF_050 CAREF_2
+#define CAREF_VT CAREF_3
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_dac12_h
+#define __msp430_headers_dac12_h
+
+/* dac12.h
+ *
+ * mspgcc project: MSP430 device headers
+ * DAC12 module header
+ *
+ * (c) 2002 by Steve Udnerwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: dac12.h,v 1.5 2004/11/03 14:29:10 coppice Exp $
+ */
+
+/* Switches: __msp430_have_dac12_op_amp */
+
+#define DAC12_0CTL_ 0x01C0 /* DAC12 control 0 */
+sfrw(DAC12_0CTL,DAC12_0CTL_);
+#define DAC12_1CTL_ 0x01C2 /* DAC12 control 1 */
+sfrw(DAC12_1CTL,DAC12_1CTL_);
+#define DAC12_0DAT_ 0x01C8 /* DAC12 data 0 */
+sfrw(DAC12_0DAT,DAC12_0DAT_);
+#define DAC12_1DAT_ 0x01CA /* DAC12 data 1 */
+sfrw(DAC12_1DAT,DAC12_1DAT_);
+
+#define DAC12GRP 0x0001 /* DAC12 group */
+#define DAC12ENC 0x0002 /* DAC12 enable conversion */
+#define DAC12IFG 0x0004 /* DAC12 interrupt flag */
+#define DAC12IE 0x0008 /* DAC12 interrupt enable */
+#define DAC12DF 0x0010 /* DAC12 data format */
+#define DAC12AMP0 0x0020 /* DAC12 amplifier bit 0 */
+#define DAC12AMP1 0x0040 /* DAC12 amplifier bit 1 */
+#define DAC12AMP2 0x0080 /* DAC12 amplifier bit 2 */
+#define DAC12IR 0x0100 /* DAC12 input reference and output range */
+#define DAC12CALON 0x0200 /* DAC12 calibration */
+#define DAC12LSEL0 0x0400 /* DAC12 load select bit 0 */
+#define DAC12LSEL1 0x0800 /* DAC12 load select bit 1 */
+#define DAC12RES 0x1000 /* DAC12 resolution */
+#define DAC12SREF0 0x2000 /* DAC12 reference bit 0 */
+#define DAC12SREF1 0x4000 /* DAC12 reference bit 1 */
+#if defined(__msp430_have_dac12_op_amp)
+#define DAC12OPS 0x8000 /* DAC12 Operation Amp. */
+#endif
+
+#define DAC12AMP_0 (0<<5) /* DAC12 amplifier 0: off, 3-state */
+#define DAC12AMP_1 (1<<5) /* DAC12 amplifier 1: off, off */
+#define DAC12AMP_2 (2<<5) /* DAC12 amplifier 2: low, low */
+#define DAC12AMP_3 (3<<5) /* DAC12 amplifier 3: low, medium */
+#define DAC12AMP_4 (4<<5) /* DAC12 amplifier 4: low, high */
+#define DAC12AMP_5 (5<<5) /* DAC12 amplifier 5: medium, medium */
+#define DAC12AMP_6 (6<<5) /* DAC12 amplifier 6: medium, high */
+#define DAC12AMP_7 (7<<5) /* DAC12 amplifier 7: high, high */
+
+#define DAC12LSEL_0 (0<<10) /* DAC12 load select 0: direct */
+#define DAC12LSEL_1 (1<<10) /* DAC12 load select 1: latched with DAT */
+#define DAC12LSEL_2 (2<<10) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
+#define DAC12LSEL_3 (3<<10) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
+
+#define DAC12SREF_0 (0<<13) /* DAC12 reference 0: Vref+ */
+#define DAC12SREF_1 (1<<13) /* DAC12 reference 1: Vref+ */
+#define DAC12SREF_2 (2<<13) /* DAC12 reference 2: Veref+ */
+#define DAC12SREF_3 (3<<13) /* DAC12 reference 3: Veref+ */
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_dma_h
+#define __msp430_headers_dma_h
+
+/* dma12.h
+ *
+ * mspgcc project: MSP430 device headers
+ * DMA module header
+ *
+ * (c) 2002 by Steve Udnerwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: dma.h,v 1.8 2008/11/07 08:28:40 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_HAS_DMAIV__ - if the device has a DMAIV register
+__MSP430_HAS_DMA_3__ - if module has 16-bit address registers
+__MSP430_HAS_DMAX_3__ - if module has 20-bit address registers (430X core)
+
+ */
+
+#define DMACTL0_ 0x0122 /* DMA module control 0 */
+sfrw(DMACTL0,DMACTL0_);
+#define DMACTL1_ 0x0124 /* DMA module control 1 */
+sfrw(DMACTL1, DMACTL1_);
+#if defined(__MSP430_HAS_DMAIV__)
+#define DMAIV_ 0x0126 /* DMA module interrupt vector word */
+sfrw(DMAIV, DMAIV_);
+#endif
+
+#if defined(__MSP430_HAS_DMA_3__)
+#define DMA0CTL_ 0x01E0 /* DMA channel 0 control */
+sfrw(DMA0CTL, DMA0CTL_);
+#define DMA0SA_ 0x01E2 /* DMA channel 0 source address */
+sfrw(DMA0SA, DMA0SA_);
+#define DMA0DA_ 0x01E4 /* DMA channel 0 destination address */
+sfrw(DMA0DA, DMA0DA_);
+#define DMA0SZ_ 0x01E6 /* DMA channel 0 transfer size */
+sfrw(DMA0SZ, DMA0SZ_);
+
+#define DMA1CTL_ 0x01E8 /* DMA channel 1 control */
+sfrw(DMA1CTL, DMA1CTL_);
+#define DMA1SA_ 0x01EA /* DMA channel 1 source address */
+sfrw(DMA1SA, DMA1SA_);
+#define DMA1DA_ 0x01EC /* DMA channel 1 destination address */
+sfrw(DMA1DA, DMA1DA_);
+#define DMA1SZ_ 0x01EE /* DMA channel 1 transfer size */
+sfrw(DMA1SZ, DMA1SZ_);
+
+#define DMA2CTL_ 0x01F0 /* DMA channel 2 control */
+sfrw(DMA2CTL, DMA2CTL_);
+#define DMA2SA_ 0x01F2 /* DMA channel 2 source address */
+sfrw(DMA2SA, DMA2SA_);
+#define DMA2DA_ 0x01F4 /* DMA channel 2 destination address */
+sfrw(DMA2DA, DMA2DA_);
+#define DMA2SZ_ 0x01F6 /* DMA channel 2 transfer size */
+sfrw(DMA2SZ, DMA2SZ_);
+#endif
+
+#if defined(__MSP430_HAS_DMAX_3__)
+#define DMA0CTL_ 0x01D0 /* DMA channel 0 control */
+sfrw(DMA0CTL, DMA0CTL_);
+#define DMA0SA_ 0x01D2 /* DMA channel 0 source address */
+sfra(DMA0SA, DMA0SA_);
+#define DMA0SAL_ 0x01D2 /* DMA channel 0 source address */
+sfrw(DMA0SAL, DMA0SAL_);
+#define DMA0DA_ 0x01D6 /* DMA channel 0 destination address */
+sfra(DMA0DA, DMA0DA_);
+#define DMA0DAL_ 0x01D6 /* DMA channel 0 destination address */
+sfrw(DMA0DAL, DMA0DAL_);
+#define DMA0SZ_ 0x01DA /* DMA channel 0 transfer size */
+sfrw(DMA0SZ, DMA0SZ_);
+
+#define DMA1CTL_ 0x01DC /* DMA channel 1 control */
+sfrw(DMA1CTL, DMA1CTL_);
+#define DMA1SA_ 0x01DE /* DMA channel 1 source address */
+sfra(DMA1SA, DMA1SA_);
+#define DMA1SAL_ 0x01DE /* DMA channel 1 source address */
+sfrw(DMA1SAL, DMA1SAL_);
+#define DMA1DA_ 0x01E2 /* DMA channel 1 destination address */
+sfrw(DMA1DA, DMA1DA_);
+#define DMA1DAL_ 0x01E2 /* DMA channel 1 destination address */
+sfrw(DMA1DAL, DMA1DAL_);
+#define DMA1SZ_ 0x01E6 /* DMA channel 1 transfer size */
+sfrw(DMA1SZ, DMA1SZ_);
+
+#define DMA2CTL_ 0x01E8 /* DMA channel 2 control */
+sfrw(DMA2CTL, DMA2CTL_);
+#define DMA2SA_ 0x01EA /* DMA channel 2 source address */
+sfra(DMA2SA, DMA2SA_);
+#define DMA2SAL_ 0x01EA /* DMA channel 2 source address */
+sfrw(DMA2SAL, DMA2SAL_);
+#define DMA2DA_ 0x01EE /* DMA channel 2 destination address */
+sfra(DMA2DA, DMA2DA_);
+#define DMA2DAL_ 0x01EE /* DMA channel 2 destination address */
+sfrw(DMA2DAL, DMA2DAL_);
+#define DMA2SZ_ 0x01F2 /* DMA channel 2 transfer size */
+sfrw(DMA2SZ, DMA2SZ_);
+#endif
+
+#define DMA0TSEL0 0x0001 /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1 0x0002 /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2 0x0004 /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3 0x0008 /* DMA channel 0 transfer select bit 3 */
+#define DMA1TSEL0 0x0010 /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1 0x0020 /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2 0x0040 /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3 0x0080 /* DMA channel 1 transfer select bit 3 */
+#define DMA2TSEL0 0x0100 /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1 0x0200 /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2 0x0400 /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3 0x0800 /* DMA channel 2 transfer select bit 3 */
+
+#define DMA0TSEL_0 (0<<0) /* DMA channel 0 transfer select 0: DMA_REQ */
+#define DMA0TSEL_1 (1<<0) /* DMA channel 0 transfer select 1: Timer_A CCRIFG.2 */
+#define DMA0TSEL_2 (2<<0) /* DMA channel 0 transfer select 2: Timer_B CCRIFG.2 */
+#define DMA0TSEL_3 (3<<0) /* DMA channel 0 transfer select 3: I2C receive */
+#define DMA0TSEL_4 (4<<0) /* DMA channel 0 transfer select 4: I2C transmit */
+#define DMA0TSEL_5 (5<<0) /* DMA channel 0 transfer select 5: DAC12.0IFG */
+#define DMA0TSEL_6 (6<<0) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */
+#define DMA0TSEL_7 (7<<0) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */
+#define DMA0TSEL_8 (8<<0) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */
+#define DMA0TSEL_9 (9<<0) /* DMA channel 0 transfer select 9: UART1 receive */
+#define DMA0TSEL_10 (10<<0) /* DMA channel 0 transfer select 10: UART1 transmit */
+#define DMA0TSEL_11 (11<<0) /* DMA channel 0 transfer select 11: Multiplier ready */
+#define DMA0TSEL_14 (14<<0) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */
+#define DMA0TSEL_15 (15<<0) /* DMA channel 0 transfer select 15: DMAE0 */
+
+#define DMA1TSEL_0 (0<<4) /* DMA channel 1 transfer select 0: DMA_REQ */
+#define DMA1TSEL_1 (1<<4) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */
+#define DMA1TSEL_2 (2<<4) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */
+#define DMA1TSEL_3 (3<<4) /* DMA channel 1 transfer select 3: I2C receive */
+#define DMA1TSEL_4 (4<<4) /* DMA channel 1 transfer select 4: I2C transmit */
+#define DMA1TSEL_5 (5<<4) /* DMA channel 1 transfer select 5: DAC12.0IFG */
+#define DMA1TSEL_6 (6<<4) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */
+#define DMA1TSEL_7 (7<<4) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */
+#define DMA1TSEL_8 (8<<4) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */
+#define DMA1TSEL_9 (9<<4) /* DMA channel 1 transfer select 9: UART1 receive */
+#define DMA1TSEL_10 (10<<4) /* DMA channel 1 transfer select 10: UART1 transmit */
+#define DMA1TSEL_11 (11<<4) /* DMA channel 1 transfer select 11: Multiplier ready */
+#define DMA1TSEL_14 (14<<4) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */
+#define DMA1TSEL_15 (15<<4) /* DMA channel 1 transfer select 15: DMAE0 */
+
+#define DMA2TSEL_0 (0<<8) /* DMA channel 2 transfer select 0: DMA_REQ */
+#define DMA2TSEL_1 (1<<8) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */
+#define DMA2TSEL_2 (2<<8) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */
+#define DMA2TSEL_3 (3<<8) /* DMA channel 2 transfer select 3: I2C receive */
+#define DMA2TSEL_4 (4<<8) /* DMA channel 2 transfer select 4: I2C transmit */
+#define DMA2TSEL_5 (5<<8) /* DMA channel 2 transfer select 5: DAC12.0IFG */
+#define DMA2TSEL_6 (6<<8) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */
+#define DMA2TSEL_7 (7<<8) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */
+#define DMA2TSEL_8 (8<<8) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */
+#define DMA2TSEL_9 (9<<8) /* DMA channel 2 transfer select 9: UART1 receive */
+#define DMA2TSEL_10 (10<<8) /* DMA channel 2 transfer select 10: UART1 transmit */
+#define DMA2TSEL_11 (11<<8) /* DMA channel 2 transfer select 11: Multiplier ready */
+#define DMA2TSEL_14 (14<<8) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */
+#define DMA2TSEL_15 (15<<8) /* DMA channel 2 transfer select 15: DMAE0 */
+
+#define ENNMI 0x0001 /* Enable NMI interruption of DMA */
+#define ROUNDROBIN 0x0002 /* Round-Robin DMA channel priorities */
+#define DMAONFETCH 0x0004 /* DMA transfer on instruction fetch */
+
+#define DMAREQ 0x0001 /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT 0x0002 /* DMA transfer aborted by NMI */
+#define DMAIE 0x0004 /* DMA interrupt enable */
+#define DMAIFG 0x0008 /* DMA interrupt flag */
+#define DMAEN 0x0010 /* DMA enable */
+#define DMALEVEL 0x0020 /* DMA level sensitive trigger select */
+#define DMASRCBYTE 0x0040 /* DMA source byte */
+#define DMADSTBYTE 0x0080 /* DMA destination byte */
+#define DMASRCINCR0 0x0100 /* DMA source increment bit 0 */
+#define DMASRCINCR1 0x0200 /* DMA source increment bit 1 */
+#define DMADSTINCR0 0x0400 /* DMA destination increment bit 0 */
+#define DMADSTINCR1 0x0800 /* DMA destination increment bit 1 */
+#define DMADT0 0x1000 /* DMA transfer mode bit 0 */
+#define DMADT1 0x2000 /* DMA transfer mode bit 1 */
+#define DMADT2 0x4000 /* DMA transfer mode bit 2 */
+
+#define DMASWDW (0<<6) /* DMA transfer: source word to destination word */
+#define DMASBDW (1<<6) /* DMA transfer: source byte to destination word */
+#define DMASWDB (2<<6) /* DMA transfer: source word to destination byte */
+#define DMASBDB (3<<6) /* DMA transfer: source byte to destination byte */
+
+#define DMASRCINCR_0 (0<<8) /* DMA source increment 0: source address unchanged */
+#define DMASRCINCR_1 (1<<8) /* DMA source increment 1: source address unchanged */
+#define DMASRCINCR_2 (2<<8) /* DMA source increment 2: source address decremented */
+#define DMASRCINCR_3 (3<<8) /* DMA source increment 3: source address incremented */
+
+#define DMADSTINCR_0 (0<<10) /* DMA destination increment 0: destination address unchanged */
+#define DMADSTINCR_1 (1<<10) /* DMA destination increment 1: destination address unchanged */
+#define DMADSTINCR_2 (2<<10) /* DMA destination increment 2: destination address decremented */
+#define DMADSTINCR_3 (3<<10) /* DMA destination increment 3: destination address incremented */
+
+#define DMADT_0 (0<<12) /* DMA transfer mode 0: single */
+#define DMADT_1 (1<<12) /* DMA transfer mode 1: block */
+#define DMADT_2 (2<<12) /* DMA transfer mode 2: interleaved */
+#define DMADT_3 (3<<12) /* DMA transfer mode 3: interleaved */
+#define DMADT_4 (4<<12) /* DMA transfer mode 4: single, repeat */
+#define DMADT_5 (5<<12) /* DMA transfer mode 5: block, repeat */
+#define DMADT_6 (6<<12) /* DMA transfer mode 6: interleaved, repeat */
+#define DMADT_7 (7<<12) /* DMA transfer mode 7: interleaved, repeat */
+
+
+/* Aliases by mspgcc */
+#define DMADT_SINGLE (0<<12) /* DMA transfer mode 0: single */
+#define DMADT_BLOCK (1<<12) /* DMA transfer mode 1: block */
+#define DMADT_INTERLEAVED (2<<12) /* DMA transfer mode 2: interleaved */
+//~ #define DMADT_3 (3<<12) /* DMA transfer mode 3: interleaved */
+#define DMADT_SINGLEREPEAT (4<<12) /* DMA transfer mode 4: single, repeat */
+#define DMADT_BLOCKREPEAT (5<<12) /* DMA transfer mode 5: block, repeat */
+#define DMADT_INTERLEAVEDREPEAT (6<<12) /* DMA transfer mode 6: interleaved, repeat */
+//~ #define DMADT_7 (7<<12) /* DMA transfer mode 7: interleaved, repeat */
+
+#define DMA0TSEL_DMA_REQ (0<<0) /* DMA channel 0 transfer select 0: DMA_REQ */
+#define DMA0TSEL_TACCR2 (1<<0) /* DMA channel 0 transfer select 1: Timer_A CCRIFG.2 */
+#define DMA0TSEL_TBCCR2 (2<<0) /* DMA channel 0 transfer select 2: Timer_B CCRIFG.2 */
+#define DMA0TSEL_I2CRX (3<<0) /* DMA channel 0 transfer select 3: I2C receive */
+#define DMA0TSEL_I2CTX (4<<0) /* DMA channel 0 transfer select 4: I2C transmit */
+#define DMA0TSEL_DAC12 (5<<0) /* DMA channel 0 transfer select 5: DAC12.0IFG */
+#define DMA0TSEL_ADC12 (6<<0) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */
+#define DMA0TSEL_TACCR0 (7<<0) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */
+#define DMA0TSEL_TBCCR0 (8<<0) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */
+#define DMA0TSEL_USART1RX (9<<0) /* DMA channel 0 transfer select 9: UART1 receive */
+#define DMA0TSEL_USART1TX (10<<0) /* DMA channel 0 transfer select 10: UART1 transmit */
+#define DMA0TSEL_MUL (11<<0) /* DMA channel 0 transfer select 11: Multiplier ready */
+//~ #define DMA0TSEL_14 (14<<0) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */
+//~ #define DMA0TSEL_15 (15<<0) /* DMA channel 0 transfer select 15: DMAE0 */
+
+#define DMA1TSEL_DMA_REQ (0<<4) /* DMA channel 1 transfer select 0: DMA_REQ */
+#define DMA1TSEL_TACCR2 (1<<4) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */
+#define DMA1TSEL_TBCCR2 (2<<4) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */
+#define DMA1TSEL_I2CRX (3<<4) /* DMA channel 1 transfer select 3: I2C receive */
+#define DMA1TSEL_I2CTX (4<<4) /* DMA channel 1 transfer select 4: I2C transmit */
+#define DMA1TSEL_DAC12 (5<<4) /* DMA channel 1 transfer select 5: DAC12.0IFG */
+#define DMA1TSEL_ADC12 (6<<4) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */
+#define DMA1TSEL_TACCR0 (7<<4) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */
+#define DMA1TSEL_TBCCR0 (8<<4) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */
+#define DMA1TSEL_USART1RX (9<<4) /* DMA channel 1 transfer select 9: UART1 receive */
+#define DMA1TSEL_USART1TX (10<<4) /* DMA channel 1 transfer select 10: UART1 transmit */
+#define DMA1TSEL_MUL (11<<4) /* DMA channel 1 transfer select 11: Multiplier ready */
+//~ #define DMA1TSEL_14 (14<<4) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */
+//~ #define DMA1TSEL_15 (15<<4) /* DMA channel 1 transfer select 15: DMAE0 */
+
+#define DMA2TSEL_DMA_REQ (0<<8) /* DMA channel 2 transfer select 0: DMA_REQ */
+#define DMA2TSEL_TACCR2 (1<<8) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */
+#define DMA2TSEL_TBCCR2 (2<<8) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */
+#define DMA2TSEL_I2CRX (3<<8) /* DMA channel 2 transfer select 3: I2C receive */
+#define DMA2TSEL_I2CTX (4<<8) /* DMA channel 2 transfer select 4: I2C transmit */
+#define DMA2TSEL_DAC12 (5<<8) /* DMA channel 2 transfer select 5: DAC12.0IFG */
+#define DMA2TSEL_ADC12 (6<<8) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */
+#define DMA2TSEL_TACCR0 (7<<8) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */
+#define DMA2TSEL_TBCCR0 (8<<8) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */
+#define DMA2TSEL_USART1RX (9<<8) /* DMA channel 2 transfer select 9: UART1 receive */
+#define DMA2TSEL_USART1TX (10<<8) /* DMA channel 2 transfer select 10: UART1 transmit */
+#define DMA2TSEL_MUL (11<<8) /* DMA channel 2 transfer select 11: Multiplier ready */
+//~ #define DMA2TSEL_14 (14<<8) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */
+//~ #define DMA2TSEL_15 (15<<8) /* DMA channel 2 transfer select 15: DMAE0 */
+
+#endif
--- /dev/null
+
+#ifndef __msp430_headers_eprom_h
+#define __msp430_headers_eprom_h
+
+/* eprom.h
+ *
+ * mspgcc project: MSP430 device headers
+ * EPROM control registers
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: eprom.h,v 1.1 2002/03/20 01:54:44 data Exp $
+ */
+
+/* Switches: none */
+
+#define EPCTL_ 0x0054 /* EPROM Control */
+sfrb (EPCTL,EPCTL_);
+#define EPEXE 0x01
+#define EPVPPS 0x02
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_esp430e_h
+#define __msp430_headers_esp430e_h
+
+/* esp430e.h
+ *
+ * mspgcc project: MSP430 device headers
+ * ESP module header
+ *
+ * (c) 2003 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: esp430e.h,v 1.6 2008/10/09 15:00:14 sb-sf Exp $
+ */
+
+/* Switches: none */
+
+#define ESPCTL_ 0x0150 /* ESP430 Control Register */
+sfrw(ESPCTL, ESPCTL_);
+#define MBCTL_ 0x0152 /* Mailbox Control Register */
+sfrw(MBCTL, MBCTL_);
+#define MBIN0_ 0x0154 /* Incoming Mailbox 0 Register */
+sfrw(MBIN0, MBIN0_);
+#define MBIN1_ 0x0156 /* Incoming Mailbox 1 Register */
+sfrw(MBIN1, MBIN1_);
+#define MBOUT0_ 0x0158 /* Outgoing Mailbox 0 Register */
+sfrw(MBOUT0, MBOUT0_);
+#define MBOUT1_ 0x015A /* Outgoing Mailbox 1 Register */
+sfrw(MBOUT1, MBOUT1_);
+
+#define RET0_ 0x01C0 /* ESP430 Return Value 0 */
+sfrw(RET0, RET0_);
+#define RET1_ 0x01C2 /* ESP430 Return Value 1 */
+sfrw(RET1, RET1_);
+#define RET2_ 0x01C4 /* ESP430 Return Value 2 */
+sfrw(RET2, RET2_);
+#define RET3_ 0x01C6 /* ESP430 Return Value 3 */
+sfrw(RET3, RET3_);
+#define RET4_ 0x01C8 /* ESP430 Return Value 4 */
+sfrw(RET4, RET4_);
+#define RET5_ 0x01CA /* ESP430 Return Value 5 */
+sfrw(RET5, RET5_);
+#define RET6_ 0x01CC /* ESP430 Return Value 6 */
+sfrw(RET6, RET6_);
+#define RET7_ 0x01CE /* ESP430 Return Value 7 */
+sfrw(RET7, RET7_);
+#define RET8_ 0x01D0 /* ESP430 Return Value 8 */
+sfrw(RET8, RET8_);
+#define RET9_ 0x01D2 /* ESP430 Return Value 9 */
+sfrw(RET9, RET9_);
+#define RET10_ 0x01D4 /* ESP430 Return Value 10 */
+sfrw(RET10, RET10_);
+#define RET11_ 0x01D6 /* ESP430 Return Value 11 */
+sfrw(RET11, RET11_);
+#define RET12_ 0x01D8 /* ESP430 Return Value 12 */
+sfrw(RET12, RET12_);
+#define RET13_ 0x01DA /* ESP430 Return Value 13 */
+sfrw(RET13, RET13_);
+#define RET14_ 0x01DC /* ESP430 Return Value 14 */
+sfrw(RET14, RET14_);
+#define RET15_ 0x01DE /* ESP430 Return Value 15 */
+sfrw(RET15, RET15_);
+#define RET16_ 0x01E0 /* ESP430 Return Value 16 */
+sfrw(RET16, RET16_);
+#define RET17_ 0x01E2 /* ESP430 Return Value 17 */
+sfrw(RET17, RET17_);
+#define RET18_ 0x01E4 /* ESP430 Return Value 18 */
+sfrw(RET18, RET18_);
+#define RET19_ 0x01E6 /* ESP430 Return Value 19 */
+sfrw(RET19, RET19_);
+#define RET20_ 0x01E8 /* ESP430 Return Value 20 */
+sfrw(RET20, RET20_);
+#define RET21_ 0x01EA /* ESP430 Return Value 21 */
+sfrw(RET21, RET21_);
+#define RET22_ 0x01EC /* ESP430 Return Value 22 */
+sfrw(RET22, RET22_);
+#define RET23_ 0x01EE /* ESP430 Return Value 23 */
+sfrw(RET23, RET23_);
+#define RET24_ 0x01F0 /* ESP430 Return Value 24 */
+sfrw(RET24, RET24_);
+#define RET25_ 0x01F2 /* ESP430 Return Value 25 */
+sfrw(RET25, RET25_);
+#define RET26_ 0x01F4 /* ESP430 Return Value 26 */
+sfrw(RET26, RET26_);
+#define RET27_ 0x01F6 /* ESP430 Return Value 27 */
+sfrw(RET27, RET27_);
+#define RET28_ 0x01F8 /* ESP430 Return Value 28 */
+sfrw(RET28, RET28_);
+#define RET29_ 0x01FA /* ESP430 Return Value 29 */
+sfrw(RET29, RET29_);
+#define RET30_ 0x01FC /* ESP430 Return Value 30 */
+sfrw(RET30, RET30_);
+#define RET31_ 0x01FE /* ESP430 Return Value 31 */
+sfrw(RET31, RET31_);
+
+#define ESP430_STAT0 RET0 /* STATUS0 of ESP430 */
+#define ESP430_STAT1 RET1 /* STATUS1 of ESP430 */
+#define WAVEFSV1 RET2 /* Waveform Sample V1 offset corrected*/
+#define WAVEFSI1 RET5 /* Waveform Sample I1 offset corrected*/
+#if defined __MSP430_HAS_ESP430E1A__
+#define WAVEFSI2 RET6 /* Waveform Sample I2 offset corrected*/
+#endif
+#define ACTENERGY1_LO RET8 /* Active energy I1 Low Word */
+#define ACTENERGY1_HI RET9 /* Active energy I1 High Word */
+#if defined __MSP430_HAS_ESP430E1A__
+#define ACTENERGY2_LO RET10 /* Active energy I2 Low Word */
+#define ACTENERGY2_HI RET11 /* Active energy I2 High Word*/
+#endif
+#define REACTENERGY_LO RET12 /* Reactive energy Low Word */
+#define REACTENERGY_HI RET13 /* Reactive energy High Word */
+#define APPENERGY_LO RET14 /* Apparent energy Low Word */
+#define APPENERGY_HI RET15 /* Apparent energy High Word */
+#define ACTENSPER1_LO RET16 /* Active energy I1 for last mains period Low Word */
+#define ACTENSPER1_HI RET17 /* Active energy I1 for last mains period High Word */
+#if defined __MSP430_HAS_ESP430E1A__
+#define ACTENSPER2_LO RET18 /* Active energy I2 for last mains period Low Word */
+#define ACTENSPER2_HI RET19 /* Active energy I2 for last mains period High Word */
+#elif defined __MSP430_HAS_ESP430E1B__
+#define IRMS_2_LO RET18 /* RMS_2 Low Word */
+#define IRMS_2_HI RET19 /* RMS_2 High Word */
+#endif
+#define POWERFCT RET20 /* Power factor */
+#define CAPIND RET21 /* Power factor: neg: inductive pos: cap. (LowByte)*/
+#define MAINSPERIOD RET22 /* Mains period */
+#define V1RMS RET23 /* Voltage RMS V1 value last second */
+#define IRMS_LO RET24 /* Current RMS value last second I1 I2 Low Word */
+#define IRMS_HI RET25 /* Current RMS value last second I1 I2 High Word */
+#define VPEAK RET26 /* Voltage V1 absolute peak value */
+#define IPEAK RET27 /* Current absolute peak value I1 I2 */
+#define LINECYCLCNT_LO RET28 /* Line cycle counter Low Word */
+#define LINECYCLCNT_HI RET29 /* Line cycle counter High Word */
+#define NMBMEAS_LO RET30 /* Number of Measurements for CPU signal Low Word */
+#define NMBMEAS_HI RET31 /* Number of Measurements for CPU signal High Word */
+
+/* ESPCTL */
+#define ESPEN (0x0001) /* ESP430 Module enable */
+#define ESPSUSP (0x0002) /* ESP430 Module suspend */
+#define IREQ (0x0004) /* NOT supported by current ESP430 Software */
+
+/* RET0 - Status0 Flags */
+#define WFSRDYFG (0x0001) /* New waveform Samples ready Flag */
+#define I2GTI1FG (0x0002) /* Current I2 greater then I1 Flag */
+#define ILREACHEDFG (0x0004) /* Interrupt level reached Flag */
+#define ENRDYFG (0x0008) /* New Energy values ready Flag */
+#define ZXLDFG (0x0010) /* Zero Crossing of V1 Flag (leading edge) */
+#define ZXTRFG (0x0020) /* Zero Crossing of V1 Flag (trailing edge) */
+#define CALRDYFG (0x0040) /* Calibration values ready Flag */
+#define TAMPFG (0x0080) /* Tampering Occured Flag */
+#define NEGENFG (0x0100) /* Negativ Energy Flag */
+#define VDROPFG (0x0200) /* Voltage drop occured Flag */
+#define VPEAKFG (0x0400) /* Voltage exceed VPeak level Flag */
+#define I1PEAKFG (0x0800) /* Current exceed I1Peak level Flag */
+#define I2PEAKFG (0x1000) /* Current exceed I2Peak level Flag */
+//#define RESERVED (0x8000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+#define ACTIVEFG (0x8000) /* Measurement or Calibration running Flag */
+
+/* MBCTL */
+#define IN0IFG (0x0001) /* Incoming Mail 0 Interrupt Flag */
+#define IN1IFG (0x0002) /* Incoming Mail 1 Interrupt Flag */
+#define OUT0FG (0x0004) /* Outgoing Mail 0 Flag */
+#define OUT1FG (0x0008) /* Outgoing Mail 1 Flag */
+#define IN0IE (0x0010) /* Incoming Mail 0 Interrupt Enable */
+#define IN1IE (0x0020) /* Incoming Mail 1 Interrupt Enable */
+#define CLR0OFF (0x0040) /* Switch off automatic clear of IN0IFG */
+#define CLR1OFF (0x0080) /* Switch off automatic clear of IN1IFG */
+#define OUT0IFG (0x0100) /* Outgoing Mail 0 Interrupt Flag */
+#define OUT1IFG (0x0200) /* Outgoing Mail 1 Interrupt Flag */
+#define OUT0IE (0x0400) /* Outgoing Mail 0 Interrupt Enable */
+#define OUT1IE (0x0800) /* Outgoing Mail 1 Interrupt Enable */
+
+/* Messages to ESP */
+#define mRESET (0x0001) /* Restart ESP430 Software */
+#define mSET_MODE (0x0003) /* Set Operation Mode for ESP430 Software */
+#define mCLR_EVENT (0x0005) /* Clear Flags for ESP430 Software */
+#define mINIT (0x0007) /* Initialize ESP430 Software */
+#define mTEMP (0x0009) /* Request Temp. Measurement from ESP430 Software */
+#define mSWVERSION (0x000B) /* Request software version of ESP430 */
+#define mREAD_PARAM (0x000D) /* Request to read the parameter with no. "Parameter No." */
+#define mREAD_I2 (0x000F) /* Request to read the I2 channel (only if not used) */
+
+#define mSET_CTRL0 (0x0200) /* Set Control Register 0 */
+#define mSET_CTRL1 (0x0202) /* Set Control Register 1 */
+#define mSET_EVENT (0x0204) /* Set which Evenets should cause an message */
+#define mSET_PHASECORR1 (0x0206) /* Set Phase Correction fo I1 */
+#define mSET_PHASECORR2 (0x0208) /* Set Phase Correction fo I2 */
+#define mSET_V1OFFSET (0x020A) /* Set Offset for V1 */
+#define mSET_I1OFFSET (0x020C) /* Set Offset for I1 */
+#define mSET_I2OFFSET (0x020E) /* Set Offset for I2 */
+#define mSET_ADAPTI1 (0x0210) /* Set Adaption factor for I1 */
+#define mSET_ADAPTI2 (0x0212) /* Set Adaption factor for I2 */
+#define mSET_GAINCORR1 (0x0214) /* Set Gain Correction for Power P1 */
+#define mSET_POFFSET1_LO (0x0216) /* Set Power Offset for Power P1 */
+#define mSET_POFFSET1_HI (0x0218) /* Set Power Offset for Power P1 */
+#define mSET_GAINCORR2 (0x021A) /* Set Gain Correction for Power P2 */
+#define mSET_POFFSET2_LO (0x021C) /* Set Power Offset for Power P2 */
+#define mSET_POFFSET2_HI (0x021E) /* Set Power Offset for Power P2 */
+#define mSET_INTRPTLEVL_LO (0x0220) /* Set Interrupt Level */
+#define mSET_INTRPTLEVL_HI (0x0222) /* Set Interrupt Level */
+#define mSET_CALCYCLCNT (0x0224) /* Set number of main cycles for calibration */
+#define mSET_STARTCURR_FRAC (0x0226) /* Set start current */
+#define mSET_STARTCURR_INT (0x0228) /* Set start current */
+#define mSET_NOMFREQ (0x022A) /* Set nominal main frequency */
+#define mSET_VDROPCYCLS (0x022C) /* Set cylces for VDrop detection */
+#define mSET_RATIOTAMP (0x022E) /* Set ratio for tamper detection */
+#define mSET_ITAMP (0x0230) /* Set minimum current for tamper detection */
+#define mSET_VDROPLEVEL (0x0232) /* Set level for VDrop detection */
+#define mSET_VPEAKLEVEL (0x0234) /* Set level for VPeak detection */
+#define mSET_IPEAKLEVEL (0x0236) /* Set level for IPeak detection */
+#define mSET_DCREMPER (0x0238) /* Set number of periods for DC-removal */
+
+/* Flags for mSET_CTRL0 */
+#define CURR_I2 (0x0001) /* 0: No I2 path, only I1 path is used */
+ /* 1: I2 path implemented (CT, dc-tol CT or shunt) */
+#define CURR_I1 (0x0002) /* 0: Current transformer, dc-tol CT or shunt */
+ /* 1: Rogowski coil (not yet implemented) */
+#define MB (0x0004) /* Intrpt to CPU: 0: energy level 1: #measurements */
+#define NE0 (0x0008) /* Neg. energy treatment: 00: clear neg. energy */
+#define NE1 (0x0010) /* 01: use absolute energy 10: use energy as it is */
+#define DCREM_V1 (0x0020) /* DC removal for V1: 0: off 1: on */
+#define DCREM_I1 (0x0040) /* DC removal for I1: 0: off 1: on */
+#define DCREM_I2 (0x0080) /* DC removal for I2: 0: off 1: on */
+
+/* Messages from ESP */
+#define mEVENT (0x0001) /* Event Status Flag for ESP430 Software */
+#define mTEMPRDY (0x0003) /* Temperature measurement completed and in MBIN1 */
+#define mSWRDY (0x0005) /* Software version in MBIN1 */
+#define mPARAMRDY (0x0007) /* Parameter requested by mREAD_PARAM returned in MBIN1 */
+#define mPARAMSET (0x0009) /* Parameter has been set */
+#define mI2RDY (0x000B) /* I2 value ready */
+
+/* EVENT: Event Message Enable Bits */
+#define WFSRDYME (0x0001) /* New waveform Samples ready */
+#define I2GTI1ME (0x0002) /* Current I2 greater then I1 */
+#define ILREACHEDME (0x0004) /* Interrupt level reached */
+#define ENRDYME (0x0008) /* New Energy values ready */
+#define ZXLDME (0x0010) /* Zero Crossing of V1 (leading edge) */
+#define ZXTRME (0x0020) /* Zero Crossing of V1 (trailing edge) */
+#define CALRDYME (0x0040) /* Calibration values ready */
+#define TAMPME (0x0080) /* Tampering Occured */
+#define NEGENME (0x0100) /* Negativ Energy */
+#define VDROPME (0x0200) /* Voltage drop occured */
+#define VPEAKME (0x0400) /* Voltage exceed VPeak level */
+#define I1PEAKME (0x0800) /* Current exceed I1Peak level */
+#define I2PEAKME (0x1000) /* Current exceed I2Peak level */
+//#define RESERVED (0x8000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+#define ACTIVEME (0x8000) /* Measurement of Calibration running */
+
+
+/* ESP Modes */
+#define modeIDLE (0x0000) /* Set Mode: Idle Mode */
+#define modeCALIBRATION (0x0002) /* Set Mode: Calibration Mode */
+#define modeMEASURE (0x0004) /* Set Mode: Measure Mode */
+#define modeRESET (0x0006) /* Set Mode: Reset and Restart the ESP430 module */
+#define modeINIT (0x0008) /* Set Mode: Initialize ESP430 module */
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_flash_h
+#define __msp430_headers_flash_h
+
+/* flash.h
+ *
+ * mspgcc project: MSP430 device headers
+ * FLASH control registers
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: flash.h,v 1.5 2005/08/17 14:28:46 coppice Exp $
+ */
+
+/* Switches:
+__MSP430_HAS_FLASH2__
+*/
+
+#define FCTL1_ 0x0128 /* FLASH Control 1 */
+sfrw (FCTL1,FCTL1_);
+#define FCTL2_ 0x012A /* FLASH Control 2 */
+sfrw (FCTL2,FCTL2_);
+#define FCTL3_ 0x012C /* FLASH Control 3 */
+sfrw (FCTL3,FCTL3_);
+
+#define FRKEY 0x9600 /* Flash key returned by read */
+#define FWKEY 0xA500 /* Flash key for write */
+#define FXKEY 0x3300 /* for use with XOR instruction */
+
+#define ERASE 0x0002 /* Enable bit for flash segment erase */
+#define MERAS 0x0004 /* Enable bit for flash mass erase */
+#if defined(__MSP430_HAS_FLASH2__)
+#define EEI 0x0008 /* Enable Erase Interrupts */
+#define EEIEX 0x0010 /* Enable Emergency Interrupt Exit */
+#endif
+#define WRT 0x0040 /* Enable bit for flash write */
+#define BLKWRT 0x0080 /* Enable bit for flash segment write */
+#define SEGWRT 0x0080 /* old definition */ /* Enable bit for Flash segment write */
+
+#define FN0 0x0001 /* Divide flash clock by: 2^0 */
+#define FN1 0x0002 /* Divide flash clock by: 2^1 */
+#define FN2 0x0004 /* Divide flash clock by: 2^2 */
+#define FN3 0x0008 /* Divide flash clock by: 2^3 */
+#define FN4 0x0010 /* Divide flash clock by: 2^4 */
+#define FN5 0x0020 /* Divide flash clock by: 2^5 */
+#define FSSEL0 0x0040 /* Flash clock select 0 */ /* to distinguish from UART SSELx */
+#define FSSEL1 0x0080 /* Flash clock select 1 */
+
+#define FSSEL_0 0x0000 /* Flash clock select: 0 - ACLK */
+#define FSSEL_1 0x0040 /* Flash clock select: 1 - MCLK */
+#define FSSEL_2 0x0080 /* Flash clock select: 2 - SMCLK */
+#define FSSEL_3 0x00C0 /* Flash clock select: 3 - SMCLK */
+
+#define BUSY 0x0001 /* Flash busy: 1 */
+#define KEYV 0x0002 /* Flash Key violation flag */
+#define ACCVIFG 0x0004 /* Flash Access violation flag */
+#define WAIT 0x0008 /* Wait flag for segment write */
+#define LOCK 0x0010 /* Lock bit: 1 - Flash is locked (read only) */
+#define EMEX 0x0020 /* Flash Emergency Exit */
+#if defined(__MSP430_HAS_FLASH2__)
+#define LOCKA 0x0040 /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
+#define FAIL 0x0080 /* Last Program or Erase failed */
+#endif
+
+/* Aliases by mspgcc */
+#define FSSEL_ACLK FSSEL_0
+#define FSSEL_MCLK FSSEL_1
+#define FSSEL_SMCLK FSSEL_2
+/*#define FSSEL_SMCLK FSSEL_3*/
+
+#endif
--- /dev/null
+#include <msp430/iostructures.h>
+
+#if !defined(__msp430_headers_gpio_h)
+#define __msp430_headers_gpio_h
+
+/* gpio.h
+ *
+ * mspgcc project: MSP430 device headers
+ * GPIO module header
+ *
+ * 2009-06-04 - THLN
+ * - for msp430x47xx
+ * - __MSP430_HAS_PORT9_R__ and __MSP430_HAS_PORT10_R__ added
+ *
+ * 2008-06-04 - TonyB (tony.borries@gmail.com)
+ * - for msp430x2618 (and possibly others)
+ * - define __MSP430_HAS_PORT7_R__ and __MSP430_HAS_PORT7_R__
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: gpio.h,v 1.8 2009/06/04 21:34:29 cliechti Exp $
+ */
+
+/* Switches:
+
+__MSP430_HAS_PORT0__ - if device has port 0
+__MSP430_HAS_PORT1__ - if device has port 1
+__MSP430_HAS_PORT1_R__ - if device has port 1 with pull-downs
+__MSP430_HAS_PORT2__ - if device has port 2
+__MSP430_HAS_PORT2_R__ - if device has port 2 with pull-downs
+__MSP430_HAS_PORT3__ - if device has port 3
+__MSP430_HAS_PORT3_R__ - if device has port 3 with pull-downs
+__MSP430_HAS_PORT4__ - if device has port 4
+__MSP430_HAS_PORT4_R__ - if device has port 4 with pull-downs
+__MSP430_HAS_PORT5__ - if device has port 5
+__MSP430_HAS_PORT5_R__ - if device has port 5 with pull-downs
+__MSP430_HAS_PORT6__ - if device has port 6
+__MSP430_HAS_PORT6_R__ - if device has port 6 with pull-downs
+__MSP430_HAS_PORT7__ - if device has port 7
+__MSP430_HAS_PORT7_R__ - if device has port 7 with pull-downs
+__MSP430_HAS_PORT8__ - if device has port 8
+__MSP430_HAS_PORT8_R__ - if device has port 8 with pull-downs
+__MSP430_HAS_PORTA__ - if device has port A (16 bit view of ports
+7 & 8)
+__MSP430_HAS_PORT9__ - if device has port 9
+__MSP430_HAS_PORT9_R__ - if device has port 9 with pull-downs
+__MSP430_HAS_PORT10__ - if device has port 10
+__MSP430_HAS_PORT10_R__ - if device has port 10 with pull-downs
+__MSP430_HAS_PORTB__ - if device has port B (16 bit view of ports
+9 & 10)
+
+Note: these only make sense if the port itself is present. Also note that
+the port resistor enable registers for ports 3-6 overlap with port 0
+registers,
+so any device that has these resistors will not have port 0.
+*/
+
+#if defined(__MSP430_HAS_PORT0__)
+#define P0IN_ 0x0010 /* Port 0 Input */
+sfrb(P0IN, P0IN_);
+#define P0IN_0 0x01
+#define P0IN_1 0x02
+#define P0IN_2 0x04
+#define P0IN_3 0x08
+#define P0IN_4 0x10
+#define P0IN_5 0x20
+#define P0IN_6 0x40
+#define P0IN_7 0x80
+
+#define P0OUT_ 0x0011 /* Port 0 Output */
+sfrb(P0OUT, P0OUT_);
+#define P0OUT_0 0x01
+#define P0OUT_1 0x02
+#define P0OUT_2 0x04
+#define P0OUT_3 0x08
+#define P0OUT_4 0x10
+#define P0OUT_5 0x20
+#define P0OUT_6 0x40
+#define P0OUT_7 0x80
+
+#define P0DIR_ 0x0012 /* Port 0 Direction */
+sfrb(P0DIR, P0DIR_);
+#define P0DIR_0 0x01
+#define P0DIR_1 0x02
+#define P0DIR_2 0x04
+#define P0DIR_3 0x08
+#define P0DIR_4 0x10
+#define P0DIR_5 0x20
+#define P0DIR_6 0x40
+#define P0DIR_7 0x80
+
+#define P0IFG_ 0x0013 /* Port 0 Interrupt Flag */
+sfrb(P0IFG, P0IFG_);
+/* These two bits are defined in Interrupt Flag 1 */
+/* #define P0IFG_0 0x01 */
+/* #define P0IFG_1 0x02 */
+#define P0IFG_2 0x04
+#define P0IFG_3 0x08
+#define P0IFG_4 0x10
+#define P0IFG_5 0x20
+#define P0IFG_6 0x40
+#define P0IFG_7 0x80
+
+#define P0IES_ 0x0014 /* Port 0 Interrupt Edge Select */
+sfrb(P0IES, P0IES_);
+#define P0IES_0 0x01
+#define P0IES_1 0x02
+#define P0IES_2 0x04
+#define P0IES_3 0x08
+#define P0IES_4 0x10
+#define P0IES_5 0x20
+#define P0IES_6 0x40
+#define P0IES_7 0x80
+
+#define P0IE_ 0x0015 /* Port 0 Interrupt Enable */
+sfrb(P0IE, P0IE_);
+/* These two bits are defined in Interrupt Enable 1 */
+/* #define P0IE_0 0x01 */
+/* #define P0IE_1 0x02 */
+#define P0IE_2 0x04
+#define P0IE_3 0x08
+#define P0IE_4 0x10
+#define P0IE_5 0x20
+#define P0IE_6 0x40
+#define P0IE_7 0x80
+#endif
+
+#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__)
+#define P1IN_ 0x0020 /* Port 1 Input */
+sfrb(P1IN, P1IN_);
+#define P1OUT_ 0x0021 /* Port 1 Output */
+sfrb(P1OUT, P1OUT_);
+#define P1DIR_ 0x0022 /* Port 1 Direction */
+sfrb(P1DIR, P1DIR_);
+#define P1IFG_ 0x0023 /* Port 1 Interrupt Flag */
+sfrb(P1IFG, P1IFG_);
+#define P1IES_ 0x0024 /* Port 1 Interrupt Edge Select */
+sfrb(P1IES, P1IES_);
+#define P1IE_ 0x0025 /* Port 1 Interrupt Enable */
+sfrb(P1IE, P1IE_);
+#define P1SEL_ 0x0026 /* Port 1 Selection */
+sfrb(P1SEL, P1SEL_);
+#if defined(__MSP430_HAS_PORT1_R__)
+#define P1REN_ 0x0027 /* Port 1 Resistor enable */
+sfrb(P1REN, P1REN_);
+#endif
+#endif
+
+#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__)
+#define P2IN_ 0x0028 /* Port 2 Input */
+sfrb(P2IN, P2IN_);
+#define P2OUT_ 0x0029 /* Port 2 Output */
+sfrb(P2OUT, P2OUT_);
+#define P2DIR_ 0x002A /* Port 2 Direction */
+sfrb(P2DIR, P2DIR_);
+#define P2IFG_ 0x002B /* Port 2 Interrupt Flag */
+sfrb(P2IFG, P2IFG_);
+#define P2IES_ 0x002C /* Port 2 Interrupt Edge Select */
+sfrb(P2IES, P2IES_);
+#define P2IE_ 0x002D /* Port 2 Interrupt Enable */
+sfrb(P2IE, P2IE_);
+#define P2SEL_ 0x002E /* Port 2 Selection */
+sfrb(P2SEL, P2SEL_);
+#if defined(__MSP430_HAS_PORT2_R__)
+#define P2REN_ 0x002F /* Port 2 Resistor enable */
+sfrb(P2REN, P2REN_);
+#endif
+#endif
+
+#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__)
+#define P3IN_ 0x0018 /* Port 3 Input */
+sfrb(P3IN, P3IN_);
+#define P3OUT_ 0x0019 /* Port 3 Output */
+sfrb(P3OUT, P3OUT_);
+#define P3DIR_ 0x001A /* Port 3 Direction */
+sfrb(P3DIR, P3DIR_);
+#define P3SEL_ 0x001B /* Port 3 Selection */
+sfrb(P3SEL, P3SEL_);
+#if defined(__MSP430_HAS_PORT3_R__)
+#define P3REN_ 0x0010 /* Port 3 Resistor enable */
+sfrb(P3REN, P3REN_);
+#endif
+#endif
+
+#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__)
+#define P4IN_ 0x001C /* Port 4 Input */
+sfrb(P4IN, P4IN_);
+#define P4OUT_ 0x001D /* Port 4 Output */
+sfrb(P4OUT, P4OUT_);
+#define P4DIR_ 0x001E /* Port 4 Direction */
+sfrb(P4DIR, P4DIR_);
+#define P4SEL_ 0x001F /* Port 4 Selection */
+sfrb(P4SEL, P4SEL_);
+#if defined(__MSP430_HAS_PORT4_R__)
+#define P4REN_ 0x0011 /* Port 4 Resistor enable */
+sfrb(P4REN, P4REN_);
+#endif
+#endif
+
+#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__)
+#define P5IN_ 0x0030 /* Port 5 Input */
+sfrb(P5IN, P5IN_);
+#define P5OUT_ 0x0031 /* Port 5 Output */
+sfrb(P5OUT, P5OUT_);
+#define P5DIR_ 0x0032 /* Port 5 Direction */
+sfrb(P5DIR, P5DIR_);
+#define P5SEL_ 0x0033 /* Port 5 Selection */
+sfrb(P5SEL, P5SEL_);
+#if defined(__MSP430_HAS_PORT5_R__)
+#define P5REN_ 0x0012 /* Port 5 Resistor enable */
+sfrb(P5REN, P5REN_);
+#endif
+#endif
+
+#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
+#define P6IN_ 0x0034 /* Port 6 Input */
+sfrb(P6IN, P6IN_);
+#define P6OUT_ 0x0035 /* Port 6 Output */
+sfrb(P6OUT, P6OUT_);
+#define P6DIR_ 0x0036 /* Port 6 Direction */
+sfrb(P6DIR, P6DIR_);
+#define P6SEL_ 0x0037 /* Port 6 Selection */
+sfrb(P6SEL, P6SEL_);
+#if defined(__MSP430_HAS_PORT6_R__)
+#define P6REN_ 0x0013 /* Port 6 Resistor enable */
+sfrb(P6REN, P6REN_);
+#endif
+#endif
+
+#if defined(__MSP430_HAS_PORT7__) || defined(__MSP430_HAS_PORT7_R__)
+#define P7IN_ 0x0038 /* Port 7 Input */
+sfrb(P7IN, P7IN_);
+#define P7OUT_ 0x003A /* Port 7 Output */
+sfrb(P7OUT, P7OUT_);
+#define P7DIR_ 0x003C /* Port 7 Direction */
+sfrb(P7DIR, P7DIR_);
+#define P7SEL_ 0x003E /* Port 7 Selection */
+sfrb(P7SEL, P7SEL_);
+#if defined(__MSP430_HAS_PORT7_R__)
+#define P7REN_ 0x0014 /* Port 7 Resistor enable */
+sfrb(P7REN, P7REN_);
+#endif
+#endif
+
+#if defined(__MSP430_HAS_PORT8__) || defined(__MSP430_HAS_PORT8_R__)
+#define P8IN_ 0x0039 /* Port 8 Input */
+sfrb(P8IN, P8IN_);
+#define P8OUT_ 0x003B /* Port 8 Output */
+sfrb(P8OUT, P8OUT_);
+#define P8DIR_ 0x003D /* Port 8 Direction */
+sfrb(P8DIR, P8DIR_);
+#define P8SEL_ 0x003F /* Port 8 Selection */
+sfrb(P8SEL, P8SEL_);
+#if defined(__MSP430_HAS_PORT8_R__)
+#define P8REN_ 0x0015 /* Port 8 Resistor enable */
+sfrb(P8REN, P8REN_);
+#endif
+#endif
+
+#if defined(__MSP430_HAS_PORTA__)
+#define PAIN_ 0x0038 /* Port A Input */
+sfrb(PAIN, PAIN_);
+#endif
+
+#if defined(__MSP430_HAS_PORT9__) || defined(__MSP430_HAS_PORT9_R__)
+#define P9IN_ 0x0008 /* Port 9 Input */
+sfrb(P9IN, P9IN_);
+#define P9OUT_ 0x000A /* Port 9 Output */
+sfrb(P9OUT, P9OUT_);
+#define P9DIR_ 0x000C /* Port 9 Direction */
+sfrb(P9DIR, P9DIR_);
+#define P9SEL_ 0x000E /* Port 9 Selection */
+sfrb(P9SEL, P9SEL_);
+
+#if defined(__MSP430_HAS_PORT9_R__)
+#define P9REN_ 0x0016 /* Port 9 Resistor enable */
+sfrb(P9REN, P9REN_);
+#endif
+
+#endif
+
+#if defined(__MSP430_HAS_PORT10__) || defined(__MSP430_HAS_PORT10_R__)
+#define P10IN_ 0x0009 /* Port 10 Input */
+sfrb(P10IN, P10IN_);
+#define P10OUT_ 0x000B /* Port 10 Output */
+sfrb(P10OUT, P10OUT_);
+#define P10DIR_ 0x000D /* Port 10 Direction */
+sfrb(P10DIR, P10DIR_);
+#define P10SEL_ 0x000F /* Port 10 Selection */
+sfrb(P10SEL, P10SEL_);
+
+#if defined(__MSP430_HAS_PORT10_R__)
+#define P10REN_ 0x0017 /* Port 10 Resistor enable */
+sfrb(P10REN, P10REN_);
+#endif
+
+#endif
+
+#if defined(__MSP430_HAS_PORTB__)
+#define PBIN_ 0x0008 /* Port B Input */
+sfrb(PBIN, PBIN_);
+#endif
+
+#endif
--- /dev/null
+#ifndef __MSP430_HEADERS_GPIO_5XXX_H
+#define __MSP430_HEADERS_GPIO_5XXX_H
+
+/* gpio_5xxx.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Digital I/O
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@sourceforge.net>
+ * Originally based in MSP430F543x datasheet (slas609)
+ * and MSP430x5xx Family User's Guide (slau208).
+ *
+ * $Id: gpio_5xxx.h,v 1.2 2008/12/07 23:00:38 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_PORT1_BASE__ - base address of PORT1 module. PORT1 present in device if defined
+__MSP430_PORT2_BASE__ - base address of PORT2 module. PORT2 present in device if defined
+__MSP430_PORT3_BASE__ - base address of PORT3 module. PORT3 present in device if defined
+__MSP430_PORT4_BASE__ - base address of PORT4 module. PORT4 present in device if defined
+__MSP430_PORT5_BASE__ - base address of PORT5 module. PORT5 present in device if defined
+__MSP430_PORT6_BASE__ - base address of PORT6 module. PORT6 present in device if defined
+__MSP430_PORT7_BASE__ - base address of PORT7 module. PORT7 present in device if defined
+__MSP430_PORT8_BASE__ - base address of PORT8 module. PORT8 present in device if defined
+__MSP430_PORT9_BASE__ - base address of PORT9 module. PORT9 present in device if defined
+__MSP430_PORT10_BASE__ - base address of PORT10 module. PORT10 present in device if defined
+__MSP430_PORT11_BASE__ - base address of PORT11 module. PORT11 present in device if defined
+__MSP430_PORTJ_BASE__ - base address of PORTJ module. PORTJ present in device if defined
+
+*/
+
+#if defined(__MSP430_PORT1_BASE__)
+#define P1IN_ __MSP430_PORT1_BASE__ + 0x00 /* Port 1 Input */
+sfrb(P1IN, P1IN_);
+#define P1OUT_ __MSP430_PORT1_BASE__ + 0x02 /* Port 1 Output */
+sfrb(P1OUT, P1OUT_);
+#define P1DIR_ __MSP430_PORT1_BASE__ + 0x04 /* Port 1 Direction */
+sfrb(P1DIR, P1DIR_);
+#define P1REN_ __MSP430_PORT1_BASE__ + 0x06 /* Port 1 Resistor enable */
+sfrb(P1REN, P1REN_);
+#define P1DS_ __MSP430_PORT1_BASE__ + 0x08 /* Port 1 Drive strength */
+sfrb(P1DS, P1DS_);
+#define P1SEL_ __MSP430_PORT1_BASE__ + 0x0A /* Port 1 Selection */
+sfrb(P1SEL, P1SEL_);
+#define P1IV_ __MSP430_PORT1_BASE__ + 0x0E /* Port 1 Interrupt vector word */
+sfrb(P1IV, P1IV_);
+#define P1IES_ __MSP430_PORT1_BASE__ + 0x18 /* Port 1 Interrupt Edge Select */
+sfrb(P1IES, P1IES_);
+#define P1IE_ __MSP430_PORT1_BASE__ + 0x1A /* Port 1 Interrupt Enable */
+sfrb(P1IE, P1IE_);
+#define P1IFG_ __MSP430_PORT1_BASE__ + 0x1C /* Port 1 Interrupt Flag */
+sfrb(P1IFG, P1IFG_);
+#endif
+
+#if defined(__MSP430_PORT2_BASE__)
+#define P2IN_ __MSP430_PORT2_BASE__ + 0x01 /* Port 2 Input */
+sfrb(P2IN, P2IN_);
+#define P2OUT_ __MSP430_PORT2_BASE__ + 0x03 /* Port 2 Output */
+sfrb(P2OUT, P2OUT_);
+#define P2DIR_ __MSP430_PORT2_BASE__ + 0x05 /* Port 2 Direction */
+sfrb(P2DIR, P2DIR_);
+#define P2REN_ __MSP430_PORT2_BASE__ + 0x07 /* Port 2 Resistor enable */
+sfrb(P2REN, P2REN_);
+#define P2DS_ __MSP430_PORT2_BASE__ + 0x09 /* Port 2 Drive strength */
+sfrb(P2DS, P2DS_);
+#define P2SEL_ __MSP430_PORT2_BASE__ + 0x0B /* Port 2 Selection */
+sfrb(P2SEL, P2SEL_);
+#define P2IV_ __MSP430_PORT2_BASE__ + 0x1E /* Port 2 Interrupt vector word */
+sfrb(P2IV, P2IV_);
+#define P2IES_ __MSP430_PORT2_BASE__ + 0x19 /* Port 2 Interrupt Edge Select */
+sfrb(P2IES, P2IES_);
+#define P2IE_ __MSP430_PORT2_BASE__ + 0x1B /* Port 2 Interrupt Enable */
+sfrb(P2IE, P2IE_);
+#define P2IFG_ __MSP430_PORT2_BASE__ + 0x1D /* Port 2 Interrupt Flag */
+sfrb(P2IFG, P2IFG_);
+#endif
+
+#if defined(__MSP430_PORT3_BASE__)
+#define P3IN_ __MSP430_PORT3_BASE__ + 0x00 /* Port 3 Input */
+sfrb(P3IN, P3IN_);
+#define P3OUT_ __MSP430_PORT3_BASE__ + 0x02 /* Port 3 Output */
+sfrb(P3OUT, P3OUT_);
+#define P3DIR_ __MSP430_PORT3_BASE__ + 0x04 /* Port 3 Direction */
+sfrb(P3DIR, P3DIR_);
+#define P3REN_ __MSP430_PORT3_BASE__ + 0x06 /* Port 3 Resistor enable */
+sfrb(P3REN, P3REN_);
+#define P3DS_ __MSP430_PORT3_BASE__ + 0x08 /* Port 3 Drive strength */
+sfrb(P3DS, P3DS_);
+#define P3SEL_ __MSP430_PORT3_BASE__ + 0x0A /* Port 3 Selection */
+sfrb(P3SEL, P3SEL_);
+#endif
+
+#if defined(__MSP430_PORT4_BASE__)
+#define P4IN_ __MSP430_PORT4_BASE__ + 0x01 /* Port 4 Input */
+sfrb(P4IN, P4IN_);
+#define P4OUT_ __MSP430_PORT4_BASE__ + 0x03 /* Port 4 Output */
+sfrb(P4OUT, P4OUT_);
+#define P4DIR_ __MSP430_PORT4_BASE__ + 0x05 /* Port 4 Direction */
+sfrb(P4DIR, P4DIR_);
+#define P4REN_ __MSP430_PORT4_BASE__ + 0x07 /* Port 4 Resistor enable */
+sfrb(P4REN, P4REN_);
+#define P4DS_ __MSP430_PORT4_BASE__ + 0x09 /* Port 4 Drive strength */
+sfrb(P4DS, P4DS_);
+#define P4SEL_ __MSP430_PORT4_BASE__ + 0x0B /* Port 4 Selection */
+sfrb(P4SEL, P4SEL_);
+#endif
+
+#if defined(__MSP430_PORT5_BASE__)
+#define P5IN_ __MSP430_PORT5_BASE__ + 0x00 /* Port 5 Input */
+sfrb(P5IN, P5IN_);
+#define P5OUT_ __MSP430_PORT5_BASE__ + 0x02 /* Port 5 Output */
+sfrb(P5OUT, P5OUT_);
+#define P5DIR_ __MSP430_PORT5_BASE__ + 0x04 /* Port 5 Direction */
+sfrb(P5DIR, P5DIR_);
+#define P5REN_ __MSP430_PORT5_BASE__ + 0x06 /* Port 5 Resistor enable */
+sfrb(P5REN, P5REN_);
+#define P5DS_ __MSP430_PORT5_BASE__ + 0x08 /* Port 5 Drive strength */
+sfrb(P5DS, P5DS_);
+#define P5SEL_ __MSP430_PORT5_BASE__ + 0x0A /* Port 5 Selection */
+sfrb(P5SEL, P5SEL_);
+#endif
+
+#if defined(__MSP430_PORT6_BASE__)
+#define P6IN_ __MSP430_PORT6_BASE__ + 0x01 /* Port 6 Input */
+sfrb(P6IN, P6IN_);
+#define P6OUT_ __MSP430_PORT6_BASE__ + 0x03 /* Port 6 Output */
+sfrb(P6OUT, P6OUT_);
+#define P6DIR_ __MSP430_PORT6_BASE__ + 0x05 /* Port 6 Direction */
+sfrb(P6DIR, P6DIR_);
+#define P6REN_ __MSP430_PORT6_BASE__ + 0x07 /* Port 6 Resistor enable */
+sfrb(P6REN, P6REN_);
+#define P6DS_ __MSP430_PORT6_BASE__ + 0x09 /* Port 6 Drive strength */
+sfrb(P6DS, P6DS_);
+#define P6SEL_ __MSP430_PORT6_BASE__ + 0x0B /* Port 6 Selection */
+sfrb(P6SEL, P6SEL_);
+#endif
+
+#if defined(__MSP430_PORT7_BASE__)
+#define P7IN_ __MSP430_PORT7_BASE__ + 0x00 /* Port 7 Input */
+sfrb(P7IN, P7IN_);
+#define P7OUT_ __MSP430_PORT7_BASE__ + 0x02 /* Port 7 Output */
+sfrb(P7OUT, P7OUT_);
+#define P7DIR_ __MSP430_PORT7_BASE__ + 0x04 /* Port 7 Direction */
+sfrb(P7DIR, P7DIR_);
+#define P7REN_ __MSP430_PORT7_BASE__ + 0x06 /* Port 7 Resistor enable */
+sfrb(P7REN, P7REN_);
+#define P7DS_ __MSP430_PORT7_BASE__ + 0x08 /* Port 7 Drive strength */
+sfrb(P7DS, P7DS_);
+#define P7SEL_ __MSP430_PORT7_BASE__ + 0x0A /* Port 7 Selection */
+sfrb(P7SEL, P7SEL_);
+#endif
+
+#if defined(__MSP430_PORT8_BASE__)
+#define P8IN_ __MSP430_PORT8_BASE__ + 0x01 /* Port 8 Input */
+sfrb(P8IN, P8IN_);
+#define P8OUT_ __MSP430_PORT8_BASE__ + 0x03 /* Port 8 Output */
+sfrb(P8OUT, P8OUT_);
+#define P8DIR_ __MSP430_PORT8_BASE__ + 0x05 /* Port 8 Direction */
+sfrb(P8DIR, P8DIR_);
+#define P8REN_ __MSP430_PORT8_BASE__ + 0x07 /* Port 8 Resistor enable */
+sfrb(P8REN, P8REN_);
+#define P8DS_ __MSP430_PORT8_BASE__ + 0x09 /* Port 8 Drive strength */
+sfrb(P8DS, P8DS_);
+#define P8SEL_ __MSP430_PORT8_BASE__ + 0x0B /* Port 8 Selection */
+sfrb(P8SEL, P8SEL_);
+#endif
+
+#if defined(__MSP430_PORT9_BASE__)
+#define P9IN_ __MSP430_PORT9_BASE__ + 0x00 /* Port 9 Input */
+sfrb(P9IN, P9IN_);
+#define P9OUT_ __MSP430_PORT9_BASE__ + 0x02 /* Port 9 Output */
+sfrb(P9OUT, P9OUT_);
+#define P9DIR_ __MSP430_PORT9_BASE__ + 0x04 /* Port 9 Direction */
+sfrb(P9DIR, P9DIR_);
+#define P9REN_ __MSP430_PORT9_BASE__ + 0x06 /* Port 9 Resistor enable */
+sfrb(P9REN, P9REN_);
+#define P9DS_ __MSP430_PORT9_BASE__ + 0x08 /* Port 9 Drive strength */
+sfrb(P9DS, P9DS_);
+#define P9SEL_ __MSP430_PORT9_BASE__ + 0x0A /* Port 9 Selection */
+sfrb(P9SEL, P9SEL_);
+#endif
+
+#if defined(__MSP430_PORT10_BASE__)
+#define P10IN_ __MSP430_PORT10_BASE__ + 0x01 /* Port 10 Input */
+sfrb(P10IN, P10IN_);
+#define P10OUT_ __MSP430_PORT10_BASE__ + 0x03 /* Port 10 Output */
+sfrb(P10OUT, P10OUT_);
+#define P10DIR_ __MSP430_PORT10_BASE__ + 0x05 /* Port 10 Direction */
+sfrb(P10DIR, P10DIR_);
+#define P10REN_ __MSP430_PORT10_BASE__ + 0x07 /* Port 10 Resistor enable */
+sfrb(P10REN, P10REN_);
+#define P10DS_ __MSP430_PORT10_BASE__ + 0x09 /* Port 10 Drive strength */
+sfrb(P10DS, P10DS_);
+#define P10SEL_ __MSP430_PORT10_BASE__ + 0x0B /* Port 10 Selection */
+sfrb(P10SEL, P10SEL_);
+#endif
+
+#if defined(__MSP430_PORT11_BASE__)
+#define P11IN_ __MSP430_PORT11_BASE__ + 0x00 /* Port 11 Input */
+sfrb(P11IN, P11IN_);
+#define P11OUT_ __MSP430_PORT11_BASE__ + 0x02 /* Port 11 Output */
+sfrb(P11OUT, P11OUT_);
+#define P11DIR_ __MSP430_PORT11_BASE__ + 0x04 /* Port 11 Direction */
+sfrb(P11DIR, P11DIR_);
+#define P11REN_ __MSP430_PORT11_BASE__ + 0x06 /* Port 11 Resistor enable */
+sfrb(P11REN, P11REN_);
+#define P11DS_ __MSP430_PORT11_BASE__ + 0x08 /* Port 11 Drive strength */
+sfrb(P11DS, P11DS_);
+#define P11SEL_ __MSP430_PORT11_BASE__ + 0x0A /* Port 11 Selection */
+sfrb(P11SEL, P11SEL_);
+#endif
+
+#if defined(__MSP430_PORTJ_BASE__)
+#define PJIN_ __MSP430_PORTJ_BASE__ + 0x00 /* Port J Input */
+sfrb(PJIN, PJIN_);
+#define PJOUT_ __MSP430_PORTJ_BASE__ + 0x02 /* Port J Output */
+sfrb(PJOUT, PJOUT_);
+#define PJDIR_ __MSP430_PORTJ_BASE__ + 0x04 /* Port J Direction */
+sfrb(PJDIR, PJDIR_);
+#define PJREN_ __MSP430_PORTJ_BASE__ + 0x06 /* Port J Resistor enable */
+sfrb(PJREN, PJREN_);
+#define PJDS_ __MSP430_PORTJ_BASE__ + 0x08 /* Port J Drive strength */
+sfrb(PJDS, PJDS_);
+#endif
+
+#endif /* __MSP430_HEADERS_GPIO5_XXX_H */
--- /dev/null
+/*
+ * $Id: iostructures.h,v 1.11 2008/10/09 15:00:14 sb-sf Exp $
+ */
+#ifndef __ASSEMBLER__
+
+#ifndef __IOSTRUCTURES_H__
+#define __IOSTRUCTURES_H__
+
+/*
+ * This declares some usefull structures
+ * which describe IO ports.
+ * (c) 2002, 2003 diwil@mail.ru
+ */
+
+#ifdef MSP430_BITFIELDS_UNSIGNED
+#define __MSP430_UNS__
+#else
+#define __MSP430_UNS__ unsigned
+#endif
+
+#ifndef __MSP430_PORT_INIT_
+#define __VOLATILE volatile
+#else
+#define __VOLATILE
+#endif
+
+typedef union port {
+ __VOLATILE __MSP430_UNS__ char reg_p;
+ __VOLATILE struct {
+ __MSP430_UNS__ char __p0:1,
+ __p1:1,
+ __p2:1,
+ __p3:1,
+ __p4:1,
+ __p5:1,
+ __p6:1,
+ __p7:1;
+ } __pin;
+} __attribute__ ((packed)) ioregister_t;
+
+#undef __MSP430_UNS__
+
+#define pin0 __pin.__p0
+#define pin1 __pin.__p1
+#define pin2 __pin.__p2
+#define pin3 __pin.__p3
+#define pin4 __pin.__p4
+#define pin5 __pin.__p5
+#define pin6 __pin.__p6
+#define pin7 __pin.__p7
+
+#define inport in.reg_p
+#define outport out.reg_p
+#define dirport dir.reg_p
+#define ifgport ifg.reg_p
+#define iesport ies.reg_p
+#define ieport ie.reg_p
+#define selport sel.reg_p
+
+#define IO_DIRPIN_INPUT 0 /* direction input */
+#define IO_DIRPIN_OUTPUT 1 /* direction output */
+
+#define IO_DIRPORT_INPUT 0
+#define IO_DIRPORT_OUTPUT 0xff
+
+#define IO_IESPIN_RISING 0 /* interrupt edge on low-to-high transition (front edge, rising edge) */
+#define IO_IESPIN_FALLING 1 /* -"- -"- high-to-low */
+
+#define IO_IESPORT_RISING 0
+#define IO_IESPORT_FALLING 0xff
+
+#define IO_IRQPIN_DISABLE 0 /* interrupt request disabled */
+#define IO_IRQPIN_ENABLE 1 /* -"- -"- enabled*/
+
+#define IO_IRQPORT_DISABLE 0
+#define IO_IRQPORT_ENABLE 0xff
+
+#define IO_PINPIN_SELECT 0 /* pin 'pin' function select */
+#define IO_ALTPIN_SELECT 1 /* alternative function select */
+
+#define IO_PINPORT_SELECT 0
+#define IO_ALTPORT_SELECT 0xff
+
+
+#ifdef __cplusplus
+#define __MSP430_EXTERN__ extern "C"
+#else
+#define __MSP430_EXTERN__
+#endif //__cplusplus
+
+/****************************************************************/
+#if defined(__MSP430_HAS_PORT0__)
+struct port0_t {
+ ioregister_t in; /* Input */
+ ioregister_t out; /* Output */
+ ioregister_t dir; /* Direction */
+ ioregister_t ifg; /* Interrupt Flag */
+ ioregister_t ies; /* Interrupt Edge Select */
+ ioregister_t ie; /* Interrupt Enable */
+};
+
+__MSP430_EXTERN__ struct port0_t port0 asm("0x0010");
+#endif
+
+/****************************************************************/
+#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT2__) \
+ || defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__)
+struct port_full_t {
+ ioregister_t in; /* Input */
+ ioregister_t out; /* Output */
+ ioregister_t dir; /* Direction */
+ ioregister_t ifg; /* Interrupt Flag */
+ ioregister_t ies; /* Interrupt Edge Select */
+ ioregister_t ie; /* Interrupt Enable */
+ ioregister_t sel; /* Selection */
+#if defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__)
+ ioregister_t ren; /* Pull up or down resistor enable */
+#endif
+};
+#endif
+
+#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT4__) \
+ || defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT6__) \
+ || defined(__MSP430_HAS_PORT3_R__) || defined(__MSP430_HAS_PORT4_R__) \
+ || defined(__MSP430_HAS_PORT5_R__) || defined(__MSP430_HAS_PORT6_R__)
+struct port_simple_t {
+ ioregister_t in; /* Input */
+ ioregister_t out; /* Output */
+ ioregister_t dir; /* Direction */
+ ioregister_t sel; /* Selection */
+};
+#endif
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
+#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__)
+__MSP430_EXTERN__ struct port_full_t port1 asm("0x0020");
+#endif
+
+#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__)
+__MSP430_EXTERN__ struct port_full_t port2 asm("0x0028");
+#endif
+
+#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__)
+__MSP430_EXTERN__ struct port_simple_t port3 asm("0x0018");
+#endif
+
+#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__)
+__MSP430_EXTERN__ struct port_simple_t port4 asm("0x001c");
+#endif
+
+#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__)
+__MSP430_EXTERN__ struct port_simple_t port5 asm("0x0030");
+#endif
+
+#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
+__MSP430_EXTERN__ struct port_simple_t port6 asm("0x0034");
+#endif
+
+#undef __MSP430_EXTERN__
+
+#ifdef __MSP430_PORT_INIT_
+#undef __VOLATILE
+#endif
+
+
+#endif /* __IOSTRUCTURES_H__ */
+
+#endif /* __ASSEMBLER__ */
+
--- /dev/null
+#ifndef __msp430_headers_lcd_h
+#define __msp430_headers_lcd_h
+
+/* lcd.h
+ *
+ * mspgcc project: MSP430 device headers
+ * LCD module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: lcd.h,v 1.7 2008/10/09 15:00:14 sb-sf Exp $
+ */
+
+/* Switches:
+
+LCD_BASE - base address of LCD module
+__msp430_have_lcdlowr - if LCD controller supports the LCDLOWR bit
+__msp430_have_lcd_16_20 - if LCD controller supports memory locations 16 to 20
+
+*/
+
+#define LCDCTL_ LCD_BASE /* LCD control */
+sfrb(LCDCTL,LCDCTL_);
+
+/* the names of the mode bits are different from the spec */
+#define LCDON 0x01
+#if defined(__msp430_have_lcdlowr)
+#define LCDLOWR 0x02
+#endif
+#define LCDSON 0x04
+#define LCDMX0 0x08
+#define LCDMX1 0x10
+#define LCDP0 0x20
+#define LCDP1 0x40
+#define LCDP2 0x80
+/* Display modes coded with Bits 2-4 */
+#define LCDSTATIC (LCDSON)
+#define LCD2MUX (LCDMX0|LCDSON)
+#define LCD3MUX (LCDMX1|LCDSON)
+#define LCD4MUX (LCDMX1|LCDMX0|LCDSON)
+/* Group select code with Bits 5-7 Seg.lines */
+#define LCDSG0 0x00 /* --------- */
+#define LCDSG0_1 (LCDP0) /* S0 - S15 */
+#define LCDSG0_2 (LCDP1) /* S0 - S19 */
+#define LCDSG0_3 (LCDP1|LCDP0) /* S0 - S23 */
+#define LCDSG0_4 (LCDP2) /* S0 - S27 */
+#define LCDSG0_5 (LCDP2|LCDP0) /* S0 - S31 */
+#define LCDSG0_6 (LCDP2|LCDP1) /* S0 - S35 */
+#define LCDSG0_7 (LCDP2|LCDP1|LCDP0) /* S0 - S39 */
+
+/* NOTE: YOU CAN ONLY USE THE 'S' OR 'G' DECLARATIONS FOR A COMMAND */
+/* MOV #LCDSG0_3+LCDOG2_7,&LCDCTL ACTUALLY MEANS MOV #LCDP1,&LCDCTL! */
+#define LCDOG1_7 0x00 /* --------- */
+#define LCDOG2_7 (LCDP0) /* S0 - S15 */
+#define LCDOG3_7 (LCDP1) /* S0 - S19 */
+#define LCDOG4_7 (LCDP1|LCDP0) /* S0 - S23 */
+#define LCDOG5_7 (LCDP2) /* S0 - S27 */
+#define LCDOG6_7 (LCDP2|LCDP0) /* S0 - S31 */
+#define LCDOG7 (LCDP2|LCDP1) /* S0 - S35 */
+#define LCDOGOFF (LCDP2|LCDP1|LCDP0) /* S0 - S39 */
+
+#define LCDMEM_ LCD_BASE+1 /* LCD memory */
+#if defined(__ASSEMBLER__)
+#define LCDMEM LCDMEM_ /* LCD memory (for assembler) */
+#else
+#define LCDMEM ((char*) LCDMEM_) /* LCD memory (for C) */
+#endif
+#define LCDM1_ LCDMEM_ /* LCD memory 1 */
+sfrb(LCDM1,LCDM1_);
+#define LCDM2_ LCD_BASE+0x2 /* LCD memory 2 */
+sfrb(LCDM2,LCDM2_);
+#define LCDM3_ LCD_BASE+0x3 /* LCD memory 3 */
+sfrb(LCDM3,LCDM3_);
+#define LCDM4_ LCD_BASE+0x4 /* LCD memory 4 */
+sfrb(LCDM4,LCDM4_);
+#define LCDM5_ LCD_BASE+0x5 /* LCD memory 5 */
+sfrb(LCDM5,LCDM5_);
+#define LCDM6_ LCD_BASE+0x6 /* LCD memory 6 */
+sfrb(LCDM6,LCDM6_);
+#define LCDM7_ LCD_BASE+0x7 /* LCD memory 7 */
+sfrb(LCDM7,LCDM7_);
+#define LCDM8_ LCD_BASE+0x8 /* LCD memory 8 */
+sfrb(LCDM8,LCDM8_);
+#define LCDM9_ LCD_BASE+0x9 /* LCD memory 9 */
+sfrb(LCDM9,LCDM9_);
+#define LCDM10_ LCD_BASE+0xA /* LCD memory 10 */
+sfrb(LCDM10,LCDM10_);
+#define LCDM11_ LCD_BASE+0xB /* LCD memory 11 */
+sfrb(LCDM11,LCDM11_);
+#define LCDM12_ LCD_BASE+0xC /* LCD memory 12 */
+sfrb(LCDM12,LCDM12_);
+#define LCDM13_ LCD_BASE+0xD /* LCD memory 13 */
+sfrb(LCDM13,LCDM13_);
+#define LCDM14_ LCD_BASE+0xE /* LCD memory 14 */
+sfrb(LCDM14,LCDM14_);
+#define LCDM15_ LCD_BASE+0xF /* LCD memory 15 */
+sfrb(LCDM15,LCDM15_);
+
+#define LCDMA_ LCDM10_ /* LCD memory A */
+sfrb(LCDMA,LCDMA_);
+#define LCDMB_ LCDM11_ /* LCD memory B */
+sfrb(LCDMB,LCDMB_);
+#define LCDMC_ LCDM12_ /* LCD memory C */
+sfrb(LCDMC,LCDMC_);
+#define LCDMD_ LCDM13_ /* LCD memory D */
+sfrb(LCDMD,LCDMD_);
+#define LCDME_ LCDM14_ /* LCD memory E */
+sfrb(LCDME,LCDME_);
+#define LCDMF_ LCDM15_ /* LCD memory F */
+sfrb(LCDMF,LCDMF_);
+
+#if defined(__msp430_have_lcd_16_20)
+#define LCDM16_ LCD_BASE+0x10 /* LCD memory 16 */
+sfrb(LCDM16,LCDM16_);
+#define LCDM17_ LCD_BASE+0x11 /* LCD memory 17 */
+sfrb(LCDM17,LCDM17_);
+#define LCDM18_ LCD_BASE+0x12 /* LCD memory 18 */
+sfrb(LCDM18,LCDM18_);
+#define LCDM19_ LCD_BASE+0x13 /* LCD memory 19 */
+sfrb(LCDM19,LCDM19_);
+#define LCDM20_ LCD_BASE+0x14 /* LCD memory 20 */
+sfrb(LCDM20,LCDM20_);
+#endif
+
+#endif
--- /dev/null
+#if !defined(__msp430_headers_lcd_a_h)
+#define __msp430_headers_lcd_a_h
+
+/* lcd_a.h
+ *
+ * mspgcc project: MSP430 device headers
+ * LCD_A module header
+ *
+ * (c) 2005 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: lcd_a.h,v 1.4 2008/10/09 15:00:14 sb-sf Exp $
+ */
+
+/* Switches: none */
+
+#define LCDACTL_ 0x0090 /* LCD_A Control Register */
+sfrb(LCDACTL, LCDACTL_);
+#define LCDON 0x01
+#define LCDSON 0x04
+#define LCDMX0 0x08
+#define LCDMX1 0x10
+#define LCDFREQ0 0x20
+#define LCDFREQ1 0x40
+#define LCDFREQ2 0x80
+
+/* Display modes coded with Bits 2-4 */
+#define LCDSTATIC (LCDSON)
+#define LCD2MUX (LCDMX0|LCDSON)
+#define LCD3MUX (LCDMX1|LCDSON)
+#define LCD4MUX (LCDMX1|LCDMX0|LCDSON)
+
+/* Frequency select code with Bits 5-7 */
+#define LCDFREQ_32 (0<<5) /* LCD Freq: ACLK divided by 32 */
+#define LCDFREQ_64 (1<<5) /* LCD Freq: ACLK divided by 64 */
+#define LCDFREQ_96 (2<<5) /* LCD Freq: ACLK divided by 96 */
+#define LCDFREQ_128 (3<<5) /* LCD Freq: ACLK divided by 128 */
+#define LCDFREQ_192 (4<<5) /* LCD Freq: ACLK divided by 192 */
+#define LCDFREQ_256 (5<<5) /* LCD Freq: ACLK divided by 256 */
+#define LCDFREQ_384 (6<<5) /* LCD Freq: ACLK divided by 384 */
+#define LCDFREQ_512 (7<<5) /* LCD Freq: ACLK divided by 512 */
+
+#define LCDAPCTL0_ 0x00AC /* LCD_A Port Control Register 0 */
+sfrb(LCDAPCTL0, LCDAPCTL0_);
+#define LCDS0 0x01 /* LCD Segment 0 to 3 Enable. */
+#define LCDS4 0x02 /* LCD Segment 4 to 7 Enable. */
+#define LCDS8 0x04 /* LCD Segment 8 to 11 Enable. */
+#define LCDS12 0x08 /* LCD Segment 12 to 15 Enable. */
+#define LCDS16 0x10 /* LCD Segment 16 to 19 Enable. */
+#define LCDS20 0x20 /* LCD Segment 20 to 23 Enable. */
+#define LCDS24 0x40 /* LCD Segment 24 to 27 Enable. */
+#define LCDS28 0x80 /* LCD Segment 28 to 31 Enable. */
+
+#define LCDAPCTL1_ 0x00AD /* LCD_A Port Control Register 1 */
+sfrb(LCDAPCTL1, LCDAPCTL1_);
+#define LCDS32 0x01 /* LCD Segment 32 to 35 Enable. */
+#define LCDS36 0x02 /* LCD Segment 36 to 39 Enable. */
+
+#define LCDAVCTL0_ 0x00AE /* LCD_A Voltage Control Register 0 */
+sfrb(LCDAVCTL0, LCDAVCTL0_);
+#define LCD2B 0x01 /* Selects 1/2 bias. */
+#define VLCDREF0 0x02 /* Selects reference voltage for regulated charge pump: 0 */
+#define VLCDREF1 0x04 /* Selects reference voltage for regulated charge pump: 1 */
+#define LCDCPEN 0x08 /* LCD Voltage Charge Pump Enable. */
+#define VLCDEXT 0x10 /* Select external source for VLCD. */
+#define LCDREXT 0x20 /* Selects external connections for LCD mid voltages. */
+#define LCDR03EXT 0x40 /* Selects external connection for lowest LCD voltage. */
+
+/* Reference voltage source select for the regulated charge pump */
+#define VLCDREF_0 (0<<1) /* Internal */
+#define VLCDREF_1 (1<<1) /* External */
+#define VLCDREF_2 (2<<1) /* Reserved */
+#define VLCDREF_3 (3<<1) /* Reserved */
+
+#define LCDAVCTL1_ 0x00AF /* LCD_A Voltage Control Register 1 */
+sfrb(LCDAVCTL1, LCDAVCTL1_);
+#define VLCD0 0x02 /* VLCD select: 0 */
+#define VLCD1 0x04 /* VLCD select: 1 */
+#define VLCD2 0x08 /* VLCD select: 2 */
+#define VLCD3 0x10 /* VLCD select: 3 */
+
+/* Charge pump voltage selections */
+#define VLCD_0 (0<<1) /* Charge pump disabled */
+#define VLCD_1 (1<<1) /* VLCD = 2.60V */
+#define VLCD_2 (2<<1) /* VLCD = 2.66V */
+#define VLCD_3 (3<<1) /* VLCD = 2.72V */
+#define VLCD_4 (4<<1) /* VLCD = 2.78V */
+#define VLCD_5 (5<<1) /* VLCD = 2.84V */
+#define VLCD_6 (6<<1) /* VLCD = 2.90V */
+#define VLCD_7 (7<<1) /* VLCD = 2.96V */
+#define VLCD_8 (8<<1) /* VLCD = 3.02V */
+#define VLCD_9 (9<<1) /* VLCD = 3.08V */
+#define VLCD_10 (10<<1) /* VLCD = 3.14V */
+#define VLCD_11 (11<<1) /* VLCD = 3.20V */
+#define VLCD_12 (12<<1) /* VLCD = 3.26V */
+#define VLCD_13 (12<<1) /* VLCD = 3.32V */
+#define VLCD_14 (13<<1) /* VLCD = 3.38V */
+#define VLCD_15 (15<<1) /* VLCD = 3.44V */
+
+#define VLCD_DISABLED (0<<1) /* Charge pump disabled */
+#define VLCD_2_60 (1<<1) /* VLCD = 2.60V */
+#define VLCD_2_66 (2<<1) /* VLCD = 2.66V */
+#define VLCD_2_72 (3<<1) /* VLCD = 2.72V */
+#define VLCD_2_78 (4<<1) /* VLCD = 2.78V */
+#define VLCD_2_84 (5<<1) /* VLCD = 2.84V */
+#define VLCD_2_90 (6<<1) /* VLCD = 2.90V */
+#define VLCD_2_96 (7<<1) /* VLCD = 2.96V */
+#define VLCD_3_02 (8<<1) /* VLCD = 3.02V */
+#define VLCD_3_08 (9<<1) /* VLCD = 3.08V */
+#define VLCD_3_14 (10<<1) /* VLCD = 3.14V */
+#define VLCD_3_20 (11<<1) /* VLCD = 3.20V */
+#define VLCD_3_26 (12<<1) /* VLCD = 3.26V */
+#define VLCD_3_32 (12<<1) /* VLCD = 3.32V */
+#define VLCD_3_38 (13<<1) /* VLCD = 3.38V */
+#define VLCD_3_44 (15<<1) /* VLCD = 3.44V */
+
+#define LCDMEM_ LCD_BASE+1 /* LCD memory */
+#ifdef __ASSEMBLER__
+#define LCDMEM LCDMEM_ /* LCD memory (for assembler) */
+#else
+#define LCDMEM ((char*) LCDMEM_) /* LCD memory (for C) */
+#endif
+#define LCDM1_ LCDMEM_ /* LCD memory 1 */
+sfrb(LCDM1,LCDM1_);
+#define LCDM2_ LCD_BASE+0x2 /* LCD memory 2 */
+sfrb(LCDM2,LCDM2_);
+#define LCDM3_ LCD_BASE+0x3 /* LCD memory 3 */
+sfrb(LCDM3,LCDM3_);
+#define LCDM4_ LCD_BASE+0x4 /* LCD memory 4 */
+sfrb(LCDM4,LCDM4_);
+#define LCDM5_ LCD_BASE+0x5 /* LCD memory 5 */
+sfrb(LCDM5,LCDM5_);
+#define LCDM6_ LCD_BASE+0x6 /* LCD memory 6 */
+sfrb(LCDM6,LCDM6_);
+#define LCDM7_ LCD_BASE+0x7 /* LCD memory 7 */
+sfrb(LCDM7,LCDM7_);
+#define LCDM8_ LCD_BASE+0x8 /* LCD memory 8 */
+sfrb(LCDM8,LCDM8_);
+#define LCDM9_ LCD_BASE+0x9 /* LCD memory 9 */
+sfrb(LCDM9,LCDM9_);
+#define LCDM10_ LCD_BASE+0xA /* LCD memory 10 */
+sfrb(LCDM10,LCDM10_);
+#define LCDM11_ LCD_BASE+0xB /* LCD memory 11 */
+sfrb(LCDM11,LCDM11_);
+#define LCDM12_ LCD_BASE+0xC /* LCD memory 12 */
+sfrb(LCDM12,LCDM12_);
+#define LCDM13_ LCD_BASE+0xD /* LCD memory 13 */
+sfrb(LCDM13,LCDM13_);
+#define LCDM14_ LCD_BASE+0xE /* LCD memory 14 */
+sfrb(LCDM14,LCDM14_);
+#define LCDM15_ LCD_BASE+0xF /* LCD memory 15 */
+sfrb(LCDM15,LCDM15_);
+
+#define LCDMA_ LCDM10_ /* LCD memory A */
+sfrb(LCDMA,LCDMA_);
+#define LCDMB_ LCDM11_ /* LCD memory B */
+sfrb(LCDMB,LCDMB_);
+#define LCDMC_ LCDM12_ /* LCD memory C */
+sfrb(LCDMC,LCDMC_);
+#define LCDMD_ LCDM13_ /* LCD memory D */
+sfrb(LCDMD,LCDMD_);
+#define LCDME_ LCDM14_ /* LCD memory E */
+sfrb(LCDME,LCDME_);
+#define LCDMF_ LCDM15_ /* LCD memory F */
+sfrb(LCDMF,LCDMF_);
+
+#if defined(__msp430_have_lcd_16_20)
+#define LCDM16_ LCD_BASE+0x10 /* LCD memory 16 */
+sfrb(LCDM16,LCDM16_);
+#define LCDM17_ LCD_BASE+0x11 /* LCD memory 17 */
+sfrb(LCDM17,LCDM17_);
+#define LCDM18_ LCD_BASE+0x12 /* LCD memory 18 */
+sfrb(LCDM18,LCDM18_);
+#define LCDM19_ LCD_BASE+0x13 /* LCD memory 19 */
+sfrb(LCDM19,LCDM19_);
+#define LCDM20_ LCD_BASE+0x14 /* LCD memory 20 */
+sfrb(LCDM20,LCDM20_);
+#endif
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_mpy_h
+#define __msp430_headers_mpy_h
+
+/* mpy.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Hardware multiplier
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: mpy.h,v 1.2 2002/12/28 06:52:37 coppice Exp $
+ */
+
+/* Switches: none */
+
+#define MPY_ 0x0130 /* Multiply Unsigned/Operand 1 */
+sfrw(MPY,MPY_);
+#define MPYS_ 0x0132 /* Multiply Signed/Operand 1 */
+sfrw(MPYS,MPYS_);
+#define MAC_ 0x0134 /* Multiply Unsigned and Accumulate/Operand 1 */
+sfrw(MAC,MAC_);
+#define MACS_ 0x0136 /* Multiply Signed and Accumulate/Operand 1 */
+sfrw(MACS,MACS_);
+#define OP2_ 0x0138 /* Operand 2 */
+sfrw(OP2,OP2_);
+#define RESLO_ 0x013A /* Result Low Word */
+sfrw(RESLO,RESLO_);
+#define RESHI_ 0x013C /* Result High Word */
+sfrw(RESHI,RESHI_);
+#define SUMEXT_ 0x013E /* Sum Extend */
+sfrw(SUMEXT,SUMEXT_);
+
+#endif
--- /dev/null
+#ifndef __MSP430_HEADERS_MPY32_H
+#define __MSP430_HEADERS_MPY32_H
+
+/* mpy.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Hardware 32-bit multiplier
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@sourceforge.net>
+ * Originally based in MSP430F543x datasheet (slas609)
+ * and MSP430x5xx Family User's Guide (slau208).
+ *
+ * $Id: mpy32.h,v 1.3 2008/12/15 12:48:20 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_MPY32_BASE__ - base address of MPY32 module
+
+*/
+#if defined(__MSP430_MPY32_BASE__)
+#define MPY_ __MSP430_MPY32_BASE__ + 0x00 /* 16-bit operand 1 - multiply */
+sfrw(MPY, MPY_);
+#define MPYS_ __MSP430_MPY32_BASE__ + 0x02 /* 16-bit operand 1 - signed multiply */
+sfrw(MPYS, MPYS_);
+#define MAC_ __MSP430_MPY32_BASE__ + 0x04 /* 16-bit operand 1 - multiply accumulate */
+sfrw(MAC, MAC_);
+#define MACS_ __MSP430_MPY32_BASE__ + 0x06 /* 16-bit operand 1 - signed multiply accumulate */
+sfrw(MACS, MACS_);
+#define OP2_ __MSP430_MPY32_BASE__ + 0x08 /* 16-bit operand 2 */
+sfrw(OP2, OP2_);
+#define RESLO_ __MSP430_MPY32_BASE__ + 0x0A /* 16x16 result low word */
+sfrw(RESLO, RESLO_);
+#define RESHI_ __MSP430_MPY32_BASE__ + 0x0C /* 16x16 result high word */
+sfrw(RESHI, RESHI_);
+#define SUMEXT_ __MSP430_MPY32_BASE__ + 0x0E /* 16x16 sum extension */
+sfrw(SUMEXT, SUMEXT_);
+#define MPY32L_ __MSP430_MPY32_BASE__ + 0x10 /* 32-bit operand 1 - multiply low word */
+sfrw(MPY32L, MPY32L_);
+#define MPY32H_ __MSP430_MPY32_BASE__ + 0x12 /* 32-bit operand 1 - multiply high word */
+sfrw(MPY32H, MPY32H_);
+#define MPYS32L_ __MSP430_MPY32_BASE__ + 0x14 /* 32-bit operand 1 - signed multiply low word */
+sfrw(MPYS32L, MPYS32L_);
+#define MPYS32H_ __MSP430_MPY32_BASE__ + 0x16 /* 32-bit operand 1 - signed multiply high word */
+sfrw(MPYS32H, MPYS32H_);
+#define MAC32L_ __MSP430_MPY32_BASE__ + 0x18 /* 32-bit operand 1 - multiply accumulate low word */
+sfrw(MAC32L, MAC32L_);
+#define MAC32H_ __MSP430_MPY32_BASE__ + 0x1A /* 32-bit operand 1 - multiply accumulate high word */
+sfrw(MAC32H, MAC32H_);
+#define MACS32L_ __MSP430_MPY32_BASE__ + 0x1C /* 32-bit operand 1 - signed multiply accumulate low word */
+sfrw(MACS32L, MACS32L_);
+#define MACS32H_ __MSP430_MPY32_BASE__ + 0x1E /* 32-bit operand 1 - signed multiply accumulate high word */
+sfrw(MACS32H, MACS32H_);
+#define OP2L_ __MSP430_MPY32_BASE__ + 0x20 /* 32-bit operand 2 - low word */
+sfrw(OP2L, OP2L_);
+#define OP2H_ __MSP430_MPY32_BASE__ + 0x22 /* 32-bit operand 2 - high word */
+sfrw(OP2H, OP2H_);
+#define RES0_ __MSP430_MPY32_BASE__ + 0x24 /* 32x32 result 3 - least significant word */
+sfrw(RES0,RES0_);
+#define RES1_ __MSP430_MPY32_BASE__ + 0x26
+sfrw(RES1,RES1_);
+#define RES2_ __MSP430_MPY32_BASE__ + 0x28
+sfrw(RES2,RES2_);
+#define RES3_ __MSP430_MPY32_BASE__ + 0x2A /* 32x32 result 3 - most significant word */
+sfrw(RES3,RES3_);
+#define MPY32CTL0_ __MSP430_MPY32_BASE__ + 0x2C /* MPY32 control register 0 */
+sfrw(MPY32CTL0,MPY32CTL0_);
+#endif /* defined(__MSP430_MPY32_BASE__) */
+
+#define MPYDLY32 (1<<9) /* Delayed write mode */
+#define MPYDLYWRTEN (1<<8) /* Delayed write enable */
+#define MPYPO2_32 (1<<7) /* Multiplier bit width of operand 2 */
+#define MPYPO1_32 (1<<6) /* Multiplier bit width of operand 1 */
+#define MPYM1 (1<<5) /* Multiplier mode */
+#define MPYM0 (1<<4) /* -- // -- */
+#define MPYSAT (1<<3) /* Saturation mode */
+#define MPYFRAC (1<<2) /* Fractional mode */
+#define MPYC (1<<0) /* Carry of the multiplier */
+
+#define MPYM_0 (0<<4) /* Multiply */
+#define MPYM_1 (1<<4) /* Signed multiply */
+#define MPYM_2 (2<<4) /* Multiply accumulate */
+#define MPYM_3 (3<<4) /* Signed multiply accumulate */
+
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+
+#undef __xstr
+#undef __str
+#define __xstr(x) __str(x)
+#define __str(x) #x
+
+typedef struct
+{
+ volatile unsigned int MPY; /* 16-bit operand 1 - multiply */
+ volatile unsigned int MPYS; /* 16-bit operand 1 - signed multiply */
+ volatile unsigned int MAC; /* 16-bit operand 1 - multiply accumulate */
+ volatile unsigned int MACS; /* 16-bit operand 1 - signed multiply accumulate */
+ volatile unsigned int OP2; /* 16-bit operand 2 */
+ volatile unsigned int RESLO; /* 16x16 result low word */
+ volatile unsigned int RESHI; /* 16x16 result high word */
+ volatile unsigned int SUMEXT; /* 16x16 sum extension */
+ volatile unsigned int MPY32L; /* 32-bit operand 1 - multiply low word */
+ volatile unsigned int MPY32H; /* 32-bit operand 1 - multiply high word */
+ volatile unsigned int MPYS32L; /* 32-bit operand 1 - signed multiply low word */
+ volatile unsigned int MPYS32H; /* 32-bit operand 1 - signed multiply high word */
+ volatile unsigned int MAC32L; /* 32-bit operand 1 - multiply accumulate low word */
+ volatile unsigned int MAC32H; /* 32-bit operand 1 - multiply accumulate high word */
+ volatile unsigned int MACS32L; /* 32-bit operand 1 - signed multiply accumulate low word */
+ volatile unsigned int MACS32H; /* 32-bit operand 1 - signed multiply accumulate high word */
+ volatile unsigned int OP2L; /* 32-bit operand 2 - low word */
+ volatile unsigned int OP2H; /* 32-bit operand 2 - high word */
+ volatile unsigned int RES0; /* 32x32 result 3 - least significant word */
+ volatile unsigned int RES1;
+ volatile unsigned int RES2;
+ volatile unsigned int RES3; /* 32x32 result 3 - most significant word */
+ volatile unsigned int MPY32CTL0; /* MPY32 control register 0 */
+} mpy32_t;
+mpy32_t mpy32 asm(__xstr(__MSP430_MPY32_BASE__));
+#undef __str
+#undef __xstr
+#endif /* __ASSEMBLER__ */
+
+#endif /* __MSP430_HEADERS_MPY32_H */
--- /dev/null
+#ifndef __msp430_headers_opamp_h
+#define __msp430_headers_opamp_h
+
+/* opamp.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Operational amplifier module header
+ *
+ * (c) 2003 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: opamp.h,v 1.6 2007/09/18 12:37:02 coppice Exp $
+ */
+
+/* Switches:
+__msp430_have_opamp_1
+__msp430_have_opamp_2
+__msp430_have_opamp_feedback_taps
+__msp430_have_opamp_switches
+__msp430_have_opamp_output_select
+__msp430_have_opamp_rail_to_rail
+__msp430_have_opamp_offset_cal
+*/
+
+#define OA0CTL0_ 0x00C0 /* OA0 Control register 0 */
+sfrb(OA0CTL0, OA0CTL0_);
+#define OA0CTL1_ 0x00C1 /* OA0 Control register 1 */
+sfrb(OA0CTL1, OA0CTL1_);
+
+#if defined(__msp430_have_opamp_1)
+#define OA1CTL0_ 0x00C2 /* OA1 Control register 0 */
+sfrb(OA1CTL0, OA1CTL0_);
+#define OA1CTL1_ 0x00C3 /* OA1 Control register 1 */
+sfrb(OA1CTL1, OA1CTL1_);
+#endif
+
+#if defined(__msp430_have_opamp_2)
+#define OA2CTL0_ 0x00C4 /* OA2 Control register 0 */
+sfrb(OA2CTL0, OA2CTL0_);
+#define OA2CTL1_ 0x00C5 /* OA2 Control register 1 */
+sfrb(OA2CTL1, OA2CTL1_);
+#endif
+
+#if defined(__msp430_have_opamp_switches)
+#define SWCTL_ 0x00CF /* OA Analog Switches Control Register */
+sfrb(SWCTL, SWCTL_)
+#endif
+
+#if defined(__msp430_have_opamp_output_select)
+#define OAADC0 0x01 /* OAx output to ADC12 input channel select 0 */
+#define OAADC1 0x02 /* OAx output to ADC12 input channel select 1 */
+#endif
+#define OAPM0 0x04 /* OAx Power mode select 0 */
+#define OAPM1 0x08 /* OAx Power mode select 1 */
+#define OAP0 0x10 /* OAx Inverting input select 0 */
+#define OAP1 0x20 /* OAx Inverting input select 1 */
+#define OAN0 0x40 /* OAx Non-inverting input select 0 */
+#define OAN1 0x80 /* OAx Non-inverting input select 1 */
+
+#define OAPM_0 (0<<2) /* OAx Power mode select: off */
+#define OAPM_1 (1<<2) /* OAx Power mode select: slow */
+#define OAPM_2 (2<<2) /* OAx Power mode select: medium */
+#define OAPM_3 (3<<2) /* OAx Power mode select: fast */
+#define OAP_0 (0<<4) /* OAx Inverting input select 00 */
+#define OAP_1 (1<<4) /* OAx Inverting input select 01 */
+#define OAP_2 (2<<4) /* OAx Inverting input select 10 */
+#define OAP_3 (3<<4) /* OAx Inverting input select 11 */
+#define OAN_0 (0<<6) /* OAx Non-inverting input select 00 */
+#define OAN_1 (1<<6) /* OAx Non-inverting input select 01 */
+#define OAN_2 (2<<6) /* OAx Non-inverting input select 10 */
+#define OAN_3 (3<<6) /* OAx Non-inverting input select 11 */
+
+#if defined(__msp430_have_opamp_rail_to_rail)
+#define OARRIP 0x01 /* OAx Rail-to-Rail Input off */
+#endif
+#if defined(__msp430_have_opamp_offset_cal)
+#define OACAL 0x02 /* OAx Offset Calibration */
+#endif
+#define OAFC0 0x04 /* OAx Function control 0 */
+#define OAFC1 0x08 /* OAx Function control 1 */
+#define OAFC2 0x10 /* OAx Function control 2 */
+#if defined(__msp430_have_opamp_feedback_taps)
+#define OAFBR0 0x20 /* OAx Feedback resistor select 0 */
+#define OAFBR1 0x40 /* OAx Feedback resistor select 1 */
+#define OAFBR2 0x80 /* OAx Feedback resistor select 2 */
+#endif
+
+#define OAFC_0 (0<<2) /* OAx Function: Gen. Purpose */
+#define OAFC_1 (1<<2) /* OAx Function: Comparing */
+#define OAFC_2 (2<<2) /* OAx Function: Reserved */
+#define OAFC_3 (3<<2) /* OAx Function: Differential */
+#define OAFC_4 (4<<2) /* OAx Function: Non-Inverting, PGA */
+#define OAFC_5 (5<<2) /* OAx Function: Reserved */
+#define OAFC_6 (6<<2) /* OAx Function: Inverting */
+#define OAFC_7 (7<<2) /* OAx Function: Differential */
+
+#if defined(__msp430_have_opamp_feedback_taps)
+#define OAFBR_0 (0<<5) /* OAx Feedback resistor: Tap 0 */
+#define OAFBR_1 (1<<5) /* OAx Feedback resistor: Tap 1 */
+#define OAFBR_2 (2<<5) /* OAx Feedback resistor: Tap 2 */
+#define OAFBR_3 (3<<5) /* OAx Feedback resistor: Tap 3 */
+#define OAFBR_4 (4<<5) /* OAx Feedback resistor: Tap 4 */
+#define OAFBR_5 (5<<5) /* OAx Feedback resistor: Tap 5 */
+#define OAFBR_6 (6<<5) /* OAx Feedback resistor: Tap 6 */
+#define OAFBR_7 (7<<5) /* OAx Feedback resistor: Tap 7 */
+#endif
+
+#if defined(__msp430_have_opamp_switches)
+#define SWCTL0 0x01 /* OA Analog Switch Control 0 */
+#define SWCTL1 0x02 /* OA Analog Switch Control 1 */
+#define SWCTL2 0x04 /* OA Analog Switch Control 2 */
+#define SWCTL3 0x08 /* OA Analog Switch Control 3 */
+#define SWCTL4 0x10 /* OA Analog Switch Control 4 */
+#define SWCTL5 0x20 /* OA Analog Switch Control 5 */
+#define SWCTL6 0x40 /* OA Analog Switch Control 6 */
+#define SWCTL7 0x80 /* OA Analog Switch Control 7 */
+#endif
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_scanif_h
+#define __msp430_headers_scanif_h
+
+/* scanif.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Scan interface module header
+ *
+ * (c) 2003 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: scanif.h,v 1.3 2008/10/09 15:00:14 sb-sf Exp $
+ */
+
+/* Switches: none */
+
+#define SIFDEBUG_ 0x01B0 /* SIF, Debug Register */
+sfrw(SIFDEBUG, SIFDEBUG_);
+#define SIFCNT_ 0x01B2 /* SIF, Counter1/2 */
+sfrw(SIFCNT, SIFCNT_);
+#define SIFTPSMV_ 0x01B4 /* SIF, Processing State Machine */
+sfrw(SIFTPSMV, SIFTPSMV_);
+#define SIFCTL0_ 0x01B6 /* SIF, Control Register 0 */
+sfrw(SIFCTL0, SIFCTL0_);
+#define SIFCTL1_ 0x01B8 /* SIF, Control Register 1 */
+sfrw(SIFCTL1, SIFCTL1_);
+#define SIFCTL2_ 0x01BA /* SIF, Control Register 2 */
+sfrw(SIFCTL2, SIFCTL2_);
+#define SIFCTL3_ 0x01BC /* SIF, Control Register 3 */
+sfrw(SIFCTL3, SIFCTL3_);
+#define SIFCTL4_ 0x01BE /* SIF, Control Register 4 */
+sfrw(SIFCTL4, SIFCTL4_);
+#define SIFDACR0_ 0x01C0 /* SIF, Digital to Analog Conv. 0 */
+sfrw(SIFDACR0, SIFDACR0_);
+#define SIFDACR1_ 0x01C2 /* SIF, Digital to Analog Conv. 1 */
+sfrw(SIFDACR1, SIFDACR1_);
+#define SIFDACR2_ 0x01C4 /* SIF, Digital to Analog Conv. 2 */
+sfrw(SIFDACR2, SIFDACR2_);
+#define SIFDACR3_ 0x01C6 /* SIF, Digital to Analog Conv. 3 */
+sfrw(SIFDACR3, SIFDACR3_);
+#define SIFDACR4_ 0x01C8 /* SIF, Digital to Analog Conv. 4 */
+sfrw(SIFDACR4, SIFDACR4_);
+#define SIFDACR5_ 0x01CA /* SIF, Digital to Analog Conv. 5 */
+sfrw(SIFDACR5, SIFDACR5_);
+#define SIFDACR6_ 0x01CC /* SIF, Digital to Analog Conv. 6 */
+sfrw(SIFDACR6, SIFDACR6_);
+#define SIFDACR7_ 0x01CE /* SIF, Digital to Analog Conv. 7 */
+sfrw(SIFDACR7, SIFDACR7_);
+
+#define SIFTSM_ 0x01D0 /* SIF, Timing State Machine 0 */
+#ifdef __ASSEMBLER__
+#define SIFTSM SIFTSM_ /* SIF, Timing State Machine (for assembler) */
+#else
+#define SIFTSM ((char*) SIFTSM_) /* SIF, Timing State Machine (for C) */
+#endif
+#define SIFTSM0_ 0x01D0 /* SIF, Timing State Machine 0 */
+sfrw(SIFTSM0, SIFTSM0_);
+#define SIFTSM1_ 0x01D2 /* SIF, Timing State Machine 1 */
+sfrw(SIFTSM1, SIFTSM1_);
+#define SIFTSM2_ 0x01D4 /* SIF, Timing State Machine 2 */
+sfrw(SIFTSM2, SIFTSM2_);
+#define SIFTSM3_ 0x01D6 /* SIF, Timing State Machine 3 */
+sfrw(SIFTSM3, SIFTSM3_);
+#define SIFTSM4_ 0x01D8 /* SIF, Timing State Machine 4 */
+sfrw(SIFTSM4, SIFTSM4_);
+#define SIFTSM5_ 0x01DA /* SIF, Timing State Machine 5 */
+sfrw(SIFTSM5, SIFTSM5_);
+#define SIFTSM6_ 0x01DC /* SIF, Timing State Machine 6 */
+sfrw(SIFTSM6, SIFTSM6_);
+#define SIFTSM7_ 0x01DE /* SIF, Timing State Machine 7 */
+sfrw(SIFTSM7, SIFTSM7_);
+#define SIFTSM8_ 0x01E0 /* SIF, Timing State Machine 8 */
+sfrw(SIFTSM8, SIFTSM8_);
+#define SIFTSM9_ 0x01E2 /* SIF, Timing State Machine 9 */
+sfrw(SIFTSM9, SIFTSM9_);
+#define SIFTSM10_ 0x01E4 /* SIF, Timing State Machine 10 */
+sfrw(SIFTSM10, SIFTSM10_);
+#define SIFTSM11_ 0x01E6 /* SIF, Timing State Machine 11 */
+sfrw(SIFTSM11, SIFTSM11_);
+#define SIFTSM12_ 0x01E8 /* SIF, Timing State Machine 12 */
+sfrw(SIFTSM12, SIFTSM12_);
+#define SIFTSM13_ 0x01EA /* SIF, Timing State Machine 13 */
+sfrw(SIFTSM13, SIFTSM13_);
+#define SIFTSM14_ 0x01EC /* SIF, Timing State Machine 14 */
+sfrw(SIFTSM14, SIFTSM14_);
+#define SIFTSM15_ 0x01EE /* SIF, Timing State Machine 15 */
+sfrw(SIFTSM15, SIFTSM15_);
+#define SIFTSM16_ 0x01F0 /* SIF, Timing State Machine 16 */
+sfrw(SIFTSM16, SIFTSM16_);
+#define SIFTSM17_ 0x01F2 /* SIF, Timing State Machine 17 */
+sfrw(SIFTSM17, SIFTSM17_);
+#define SIFTSM18_ 0x01F4 /* SIF, Timing State Machine 18 */
+sfrw(SIFTSM18, SIFTSM18_);
+#define SIFTSM19_ 0x01F6 /* SIF, Timing State Machine 19 */
+sfrw(SIFTSM19, SIFTSM19_);
+#define SIFTSM20_ 0x01F8 /* SIF, Timing State Machine 20 */
+sfrw(SIFTSM20, SIFTSM20_);
+#define SIFTSM21_ 0x01FA /* SIF, Timing State Machine 21 */
+sfrw(SIFTSM21, SIFTSM21_);
+#define SIFTSM22_ 0x01FC /* SIF, Timing State Machine 22 */
+sfrw(SIFTSM22, SIFTSM22_);
+#define SIFTSM23_ 0x01FE /* SIF, Timing State Machine 23 */
+sfrw(SIFTSM23, SIFTSM23_);
+
+/* SIFCTL1 */
+#define SIFEN (0x0001) /* SIF Enable */
+#define SIFTESTD (0x0002) /* SIF 0:Normal / 1:Test Mode */
+#define SIFIFG0 (0x0004) /* SIF Interrupt Flag 0 */
+#define SIFIFG1 (0x0008) /* SIF Interrupt Flag 1 */
+#define SIFIFG2 (0x0010) /* SIF Interrupt Flag 2 */
+#define SIFIFG3 (0x0020) /* SIF Interrupt Flag 3 */
+#define SIFIFG4 (0x0040) /* SIF Interrupt Flag 4 */
+#define SIFIFG5 (0x0080) /* SIF Interrupt Flag 5 */
+#define SIFIFG6 (0x0100) /* SIF Interrupt Flag 6 */
+#define SIFIE0 (0x0200) /* SIF Interrupt Enable 0 */
+#define SIFIE1 (0x0400) /* SIF Interrupt Enable 1 */
+#define SIFIE2 (0x0800) /* SIF Interrupt Enable 2 */
+#define SIFIE3 (0x1000) /* SIF Interrupt Enable 3 */
+#define SIFIE4 (0x2000) /* SIF Interrupt Enable 4 */
+#define SIFIE5 (0x4000) /* SIF Interrupt Enable 5 */
+#define SIFIE6 (0x8000) /* SIF Interrupt Enable 6 */
+
+/* SIFCTL2 */
+#define SIFTCH0OUT (0x0001) /* SIF TCH0 result */
+#define SIFTCH1OUT (0x0002) /* SIF TCH1 result */
+#define SIFTCH00 (0x0004) /* SIF 1. Channel select 0 */
+#define SIFTCH01 (0x0008) /* SIF 1. Channel select 1 */
+#define SIFTCH10 (0x0010) /* SIF 2. Channel select 0 */
+#define SIFTCH11 (0x0020) /* SIF 2. Channel select 1 */
+#define SIFTEN (0x0040) /* SIF Enable Transistors */
+#define SIFSH (0x0080) /* SIF Sample on/off */
+#define SIFVCC2 (0x0100) /* SIF VCC/2 Generator off/on */
+#define SIFVSS (0x0200) /* SIF Select Terminal for sample Cap. */
+#define SIFCACI3 (0x0400) /* SIF Selection of SIFCI3 */
+#define SIFCI3SEL (0x0800) /* SIF Select CI3 Source */
+#define SIFCAX (0x1000) /* SIF Select CA Source */
+#define SIFCAINV (0x2000) /* SIF Invert CA Output 0:off/1:on */
+#define SIFCAON (0x4000) /* SIF Switch CA on */
+#define SIFDACON (0x8000) /* SIF Switch DAC on */
+
+/* SIFCTL3 */
+#define SIF0OUT (0x0001) /* SIF Sensor 0 Out */
+#define SIF1OUT (0x0002) /* SIF Sensor 1 Out */
+#define SIF2OUT (0x0004) /* SIF Sensor 2 Out */
+#define SIF3OUT (0x0008) /* SIF Sensor 3 Out */
+#define SIFIFGSET0 (0x0010) /* SIF SIFIFG0 level select */
+#define SIFIFGSET1 (0x0020) /* SIF SIFIFG1 level select */
+#define SIFIFGSET2 (0x0040) /* SIF SIFIFG2 level select */
+#define SIFCS (0x0080) /* SIF Capture Select */
+#define SIFIS10 (0x0100) /* SIF Input Select SIFCNT1.0 */
+#define SIFIS11 (0x0200) /* SIF Input Select SIFCNT1.1 */
+#define SIFIS20 (0x0400) /* SIF Input Select SIFCNT2.0 */
+#define SIFIS21 (0x0800) /* SIF Input Select SIFCNT2.1 */
+#define SIFIS30 (0x1000) /* SIF Input Select SIFCNT3.0 */
+#define SIFIS31 (0x2000) /* SIF Input Select SIFCNT3.1 */
+#define SIFIS40 (0x4000) /* SIF Input Select SIFCNT4.0 */
+#define SIFIS41 (0x8000) /* SIF Input Select SIFCNT4.1 */
+
+#define SIFIS1_0 (0x0000) /* SIF Input Select SIFCNT1 0 */
+#define SIFIS1_1 (0x0100) /* SIF Input Select SIFCNT1 1 */
+#define SIFIS1_2 (0x0200) /* SIF Input Select SIFCNT1 2 */
+#define SIFIS1_3 (0x0300) /* SIF Input Select SIFCNT1 3 */
+#define SIFIS2_0 (0x0000) /* SIF Input Select SIFCNT2 0 */
+#define SIFIS2_1 (0x0400) /* SIF Input Select SIFCNT2 1 */
+#define SIFIS2_2 (0x0800) /* SIF Input Select SIFCNT2 2 */
+#define SIFIS2_3 (0x0C00) /* SIF Input Select SIFCNT2 3 */
+#define SIFIS3_0 (0x0000) /* SIF Input Select SIFCNT3 0 */
+#define SIFIS3_1 (0x1000) /* SIF Input Select SIFCNT3 1 */
+#define SIFIS3_2 (0x2000) /* SIF Input Select SIFCNT3 2 */
+#define SIFIS3_3 (0x3000) /* SIF Input Select SIFCNT3 3 */
+#define SIFIS4_0 (0x0000) /* SIF Input Select SIFCNT4 0 */
+#define SIFIS4_1 (0x4000) /* SIF Input Select SIFCNT4 1 */
+#define SIFIS4_2 (0x8000) /* SIF Input Select SIFCNT4 2 */
+#define SIFIS4_3 (0xC000) /* SIF Input Select SIFCNT4 3 */
+
+/* SIFCTL4 */
+#define SIFDIV10 (0x0001) /* SIF Clock Divider 1.0 */
+#define SIFDIV11 (0x0002) /* SIF Clock Divider 1.1 */
+#define SIFDIV20 (0x0004) /* SIF Clock Divider 2.0 */
+#define SIFDIV21 (0x0008) /* SIF Clock Divider 2.1 */
+#define SIFDIV30 (0x0010) /* SIF Clock Divider 3.0 */
+#define SIFDIV31 (0x0020) /* SIF Clock Divider 3.1 */
+#define SIFDIV32 (0x0040) /* SIF Clock Divider 3.2 */
+#define SIFDIV33 (0x0080) /* SIF Clock Divider 3.3 */
+#define SIFDIV34 (0x0100) /* SIF Clock Divider 3.4 */
+#define SIFDIV35 (0x0200) /* SIF Clock Divider 3.5 */
+#define SIFQ6EN (0x0400) /* SIF Feedback 6 Enable */
+#define SIFQ7EN (0x0800) /* SIF Feedback 7 Enable */
+#define SIFCNT1ENP (0x1000) /* SIF Enable SIFCNT1 up count */
+#define SIFCNT1ENM (0x2000) /* SIF Enable SIFCNT1 down count */
+#define SIFCNT2EN (0x4000) /* SIF Enable SIFCNT2 count */
+#define SIFCNTRST (0x8000) /* SIF Enable Counter Reset on Read */
+
+#define SIFDIV1_1 (0x0000) /* SIF Clock Divider 1: /1 */
+#define SIFDIV1_2 (0x0001) /* SIF Clock Divider 1: /2 */
+#define SIFDIV1_4 (0x0002) /* SIF Clock Divider 1: /4 */
+#define SIFDIV1_8 (0x0003) /* SIF Clock Divider 1: /8 */
+#define SIFDIV2_1 (0x0000) /* SIF Clock Divider 2: /1 */
+#define SIFDIV2_2 (0x0004) /* SIF Clock Divider 2: /2 */
+#define SIFDIV2_4 (0x0008) /* SIF Clock Divider 2: /4 */
+#define SIFDIV2_8 (0x000C) /* SIF Clock Divider 2: /8 */
+
+#define SIFDIV3_1 (0x0000) /* SIF Clock Divider 3: /1 */
+#define SIFDIV3_3 (0x0010) /* SIF Clock Divider 3: /3 */
+#define SIFDIV3_5 (0x0020) /* SIF Clock Divider 3: /5 */
+#define SIFDIV3_7 (0x0030) /* SIF Clock Divider 3: /7 */
+#define SIFDIV3_9 (0x0040) /* SIF Clock Divider 3: /9 */
+#define SIFDIV3_11 (0x0050) /* SIF Clock Divider 3: /11 */
+#define SIFDIV3_13 (0x0060) /* SIF Clock Divider 3: /13 */
+#define SIFDIV3_15 (0x0070) /* SIF Clock Divider 3: /15 */
+#define SIFDIV3_21 (0x00B0) /* SIF Clock Divider 3: /21 */
+#define SIFDIV3_25 (0x0120) /* SIF Clock Divider 3: /25 */
+#define SIFDIV3_27 (0x00C0) /* SIF Clock Divider 3: /27 */
+#define SIFDIV3_33 (0x00E0) /* SIF Clock Divider 3: /33 */
+#define SIFDIV3_35 (0x00D0) /* SIF Clock Divider 3: /35 */
+#define SIFDIV3_39 (0x00E0) /* SIF Clock Divider 3: /39 */
+#define SIFDIV3_45 (0x00F0) /* SIF Clock Divider 3: /45 */
+#define SIFDIV3_49 (0x01B0) /* SIF Clock Divider 3: /49 */
+#define SIFDIV3_55 (0x0150) /* SIF Clock Divider 3: /55 */
+#define SIFDIV3_63 (0x01C0) /* SIF Clock Divider 3: /63 */
+#define SIFDIV3_65 (0x0160) /* SIF Clock Divider 3: /65 */
+#define SIFDIV3_75 (0x0170) /* SIF Clock Divider 3: /75 */
+#define SIFDIV3_77 (0x01D0) /* SIF Clock Divider 3: /77 */
+#define SIFDIV3_81 (0x0240) /* SIF Clock Divider 3: /81 */
+#define SIFDIV3_91 (0x01E0) /* SIF Clock Divider 3: /91 */
+#define SIFDIV3_99 (0x0250) /* SIF Clock Divider 3: /99 */
+#define SIFDIV3_105 (0x01F0) /* SIF Clock Divider 3: /105 */
+#define SIFDIV3_117 (0x0260) /* SIF Clock Divider 3: /117 */
+#define SIFDIV3_121 (0x02D0) /* SIF Clock Divider 3: /121 */
+#define SIFDIV3_135 (0x01F0) /* SIF Clock Divider 3: /135 */
+#define SIFDIV3_143 (0x02E0) /* SIF Clock Divider 3: /143 */
+#define SIFDIV3_165 (0x02F0) /* SIF Clock Divider 3: /165 */
+#define SIFDIV3_169 (0x0360) /* SIF Clock Divider 3: /169 */
+#define SIFDIV3_195 (0x0370) /* SIF Clock Divider 3: /195 */
+#define SIFDIV3_225 (0x03F0) /* SIF Clock Divider 3: /225 */
+
+/* SIFCTL5 */
+#define SIFCLKEN (0x0001) /* SIF 0:SMCLK for SIFCLK / 1:SIFCLKG for SIFCLK */
+#define SIFCLKGON (0x0002) /* SIF Switch SIFCLKG on */
+#define SIFFNOM (0x0004) /* SIF Select Nominal Frequ. 0:4MHz / 1:1MHz */
+#define SIFCLKFQ0 (0x0008) /* SIF Clock Generator frequency adjust 0 */
+#define SIFCLKFQ1 (0x0010) /* SIF Clock Generator frequency adjust 1 */
+#define SIFCLKFQ2 (0x0020) /* SIF Clock Generator frequency adjust 2 */
+#define SIFCLKFQ3 (0x0040) /* SIF Clock Generator frequency adjust 3 */
+#define SIFTSMRP (0x0080) /* SIF Timing State Machine Repeat mode */
+#define SIFCNT30 (0x0100) /* SIF Counter 3.0 */
+#define SIFCNT31 (0x0200) /* SIF Counter 3.1 */
+#define SIFCNT32 (0x0400) /* SIF Counter 3.2 */
+#define SIFCNT33 (0x0800) /* SIF Counter 3.3 */
+#define SIFCNT34 (0x1000) /* SIF Counter 3.4 */
+#define SIFCNT35 (0x2000) /* SIF Counter 3.5 */
+#define SIFCNT36 (0x4000) /* SIF Counter 3.6 */
+#define SIFCNT37 (0x8000) /* SIF Counter 3.7 */
+
+/* SIFTSM */
+#define SIFTSMCH0 (0x0001) /* SIF Select channel for tsm: 0 */
+#define SIFTSMCH1 (0x0002) /* SIF Select channel for tsm: 1 */
+#define SIFTSMLCOFF (0x0004) /* SIF Switch LC off */
+#define SIFTSMEX (0x0008) /* SIF */
+#define SIFTSMCA (0x0010) /* SIF */
+#define SIFTSMCLKON (0x0020) /* SIF */
+#define SIFTSMRSON (0x0040) /* SIF */
+#define SIFTSMTESTS1 (0x0080) /* SIF */
+#define SIFTSMDAC (0x0100) /* SIF */
+#define SIFTSMSTOP (0x0200) /* SIF */
+#define SIFTSMACLK (0x0400) /* SIF */
+#define SIFTSMREPEAT0 (0x0800) /* SIF */
+#define SIFTSMREPEAT1 (0x1000) /* SIF */
+#define SIFTSMREPEAT2 (0x2000) /* SIF */
+#define SIFTSMREPEAT3 (0x4000) /* SIF */
+#define SIFTSMREPEAT4 (0x8000) /* SIF */
+
+#endif
--- /dev/null
+#if !defined(__msp430_headers_sd16_h__)
+#define __msp430_headers_sd16_h__
+
+/* sd16.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Sigma Delta 16 module header
+ *
+ * (c) 2003 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: sd16.h,v 1.10 2009/01/11 23:11:48 sb-sf Exp $
+ */
+
+/* Switches:
+__MSP430_SD16IV_BASE__ - SD16IV register address
+__MSP430_SD16MEM_BASE__ - SD16MEM0 register address
+
+__MSP430_HAS_SD16_A__ - the SD16 is the "A" type
+__MSP430_HAS_SD16_BUF__ - the SD16(_A) has input buffer and SD16AE reg.
+__MSP430_HAS_SD16_CH1__ - the SD16(_A) has channel 1
+__MSP430_HAS_SD16_CH2__ - the SD16(_A) has channel 2
+__MSP430_HAS_SD16_CH3__ - the SD16(_A) has channel 3
+*/
+
+#define SD16CTL_ 0x0100 /* Sigma Delta ADC 16 Control Register */
+sfrw(SD16CTL, SD16CTL_);
+#define SD16IV_ __MSP430_SD16IV_BASE__ /* SD16 Interrupt Vector Register */
+sfrw(SD16IV, SD16IV_);
+
+#if defined(__MSP430_HAS_SD16_A__)
+#if defined(__MSP430_HAS_SD16_BUF__)
+#define SD16AE_ 0x00B7 /* SD16 Analog Input Enable Register */
+sfrb(SD16AE, SD16AE_);
+#endif
+#else
+#define SD16CONF0_ 0x00B7 /* SD16 Internal Configuration Register 0 */
+sfrb(SD16CONF0, SD16CONF0_);
+#define SD16CONF1_ 0x00BF /* SD16 Internal Configuration Register 1 */
+sfrb(SD16CONF1, SD16CONF1_);
+ /* Please use only the recommended settings */
+#endif
+
+#define SD16INCTL0_ 0x00B0 /* SD16 Input Control Register Channel 0 */
+sfrb(SD16INCTL0, SD16INCTL0_);
+#define SD16PRE0_ 0x00B8 /* SD16 Preload Register Channel 0 */
+sfrb(SD16PRE0, SD16PRE0_);
+#define SD16CCTL0_ 0x0102 /* SD16 Channel 0 Control Register */
+sfrw(SD16CCTL0, SD16CCTL0_);
+#define SD16MEM0_ __MSP430_SD16MEM_BASE__ + 0x00 /* SD16 Channel 0 Conversion Memory */
+sfrw(SD16MEM0, SD16MEM0_);
+
+#if defined(__MSP430_HAS_SD16_CH1__)
+#define SD16INCTL1_ 0x00B1 /* SD16 Input Control Register Channel 1 */
+sfrb(SD16INCTL1, SD16INCTL1_);
+#define SD16PRE1_ 0x00B9 /* SD16 Preload Register Channel 1 */
+sfrb(SD16PRE1, SD16PRE1_);
+#define SD16CCTL1_ 0x0104 /* SD16 Channel 1 Control Register */
+sfrw(SD16CCTL1, SD16CCTL1_);
+#define SD16MEM1_ __MSP430_SD16MEM_BASE__ + 0x02 /* SD16 Channel 1 Conversion Memory */
+sfrw(SD16MEM1, SD16MEM1_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_CH2__)
+#define SD16INCTL2_ 0x00B2 /* SD16 Input Control Register Channel 2 */
+sfrb(SD16INCTL2, SD16INCTL2_);
+#define SD16PRE2_ 0x00BA /* SD16 Preload Register Channel 2 */
+sfrb(SD16PRE2, SD16PRE2_);
+#define SD16CCTL2_ 0x0106 /* SD16 Channel 2 Control Register */
+sfrw(SD16CCTL2, SD16CCTL2_);
+#define SD16MEM2_ __MSP430_SD16MEM_BASE__ + 0x04 /* SD16 Channel 2 Conversion Memory */
+sfrw(SD16MEM2, SD16MEM2_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_CH3__)
+#define SD16INCTL3_ 0x00B3 /* SD16 Input Control Register Channel 3 */
+sfrb(SD16INCTL3, SD16INCTL3_);
+#define SD16PRE3_ 0x00BB /* SD16 Preload Register Channel 3 */
+sfrb(SD16PRE3, SD16PRE3_);
+#define SD16CCTL3_ 0x0108 /* SD16 Channel 3 Control Register */
+sfrw(SD16CCTL3, SD16CCTL3_);
+#define SD16MEM3_ __MSP430_SD16MEM_BASE__ + 0x06 /* SD16 Channel 3 Conversion Memory */
+sfrw(SD16MEM3, SD16MEM3_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_CH4__)
+#define SD16INCTL4_ 0x00B4 /* SD16 Input Control Register Channel 4 */
+sfrb(SD16INCTL4, SD16INCTL4_);
+#define SD16PRE4_ 0x00BC /* SD16 Preload Register Channel 4 */
+sfrb(SD16PRE4, SD16PRE4_);
+#define SD16CCTL4_ 0x010A /* SD16 Channel 4 Control Register */
+sfrw(SD16CCTL4, SD16CCTL4_);
+#define SD16MEM4_ __MSP430_SD16MEM_BASE__ + 0x08 /* SD16 Channel 4 Conversion Memory */
+sfrw(SD16MEM4, SD16MEM4_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_CH5__)
+#define SD16INCTL5_ 0x00B5 /* SD16 Input Control Register Channel 5 */
+sfrb(SD16INCTL5, SD16INCTL5_);
+#define SD16PRE5_ 0x00BD /* SD16 Preload Register Channel 5 */
+sfrb(SD16PRE5, SD16PRE5_);
+#define SD16CCTL5_ 0x010C /* SD16 Channel 5 Control Register */
+sfrw(SD16CCTL5, SD16CCTL5_);
+#define SD16MEM5_ __MSP430_SD16MEM_BASE__ + 0x0A /* SD16 Channel 5 Conversion Memory */
+sfrw(SD16MEM5, SD16MEM5_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_CH6__)
+#define SD16INCTL6_ 0x00B6 /* SD16 Input Control Register Channel 6 */
+sfrb(SD16INCTL6, SD16INCTL6_);
+#define SD16PRE6_ 0x00BE /* SD16 Preload Register Channel 6 */
+sfrb(SD16PRE6, SD16PRE6_);
+#define SD16CCTL6_ 0x010E /* SD16 Channel 6 Control Register */
+sfrw(SD16CCTL6, SD16CCTL6_);
+#define SD16MEM6_ __MSP430_SD16MEM_BASE__ + 0x0C /* SD16 Channel 6 Conversion Memory */
+sfrw(SD16MEM6, SD16MEM6_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_A__)
+/* SD16AE */
+#define SD16AE0 0x0001 /* SD16 External Input Enable 0 */
+#define SD16AE1 0x0002 /* SD16 External Input Enable 1 */
+#define SD16AE2 0x0004 /* SD16 External Input Enable 2 */
+#define SD16AE3 0x0008 /* SD16 External Input Enable 3 */
+#define SD16AE4 0x0010 /* SD16 External Input Enable 4 */
+#define SD16AE5 0x0020 /* SD16 External Input Enable 5 */
+#define SD16AE6 0x0040 /* SD16 External Input Enable 6 */
+#define SD16AE7 0x0080 /* SD16 External Input Enable 7 */
+#endif
+
+/* SD16INCTLx - AFEINCTLx */
+#define SD16INCH0 0x0001 /* SD16 Input Channel select 0 */
+#define SD16INCH1 0x0002 /* SD16 Input Channel select 1 */
+#define SD16INCH2 0x0004 /* SD16 Input Channel select 2 */
+#define SD16GAIN0 0x0008 /* AFE Input Pre-Amplifier Gain Select 0 */
+#define SD16GAIN1 0x0010 /* AFE Input Pre-Amplifier Gain Select 1 */
+#define SD16GAIN2 0x0020 /* AFE Input Pre-Amplifier Gain Select 2 */
+#define SD16INTDLY0 0x0040 /* SD16 Interrupt Delay after 1.Conversion 0 */
+#define SD16INTDLY1 0x0080 /* SD16 Interrupt Delay after 1.Conversion 1 */
+
+#define SD16GAIN_1 (0<<3) /* AFE Input Pre-Amplifier Gain Select *1 */
+#define SD16GAIN_2 (1<<3) /* AFE Input Pre-Amplifier Gain Select *2 */
+#define SD16GAIN_4 (2<<3) /* AFE Input Pre-Amplifier Gain Select *4 */
+#define SD16GAIN_8 (3<<3) /* AFE Input Pre-Amplifier Gain Select *8 */
+#define SD16GAIN_16 (4<<3) /* AFE Input Pre-Amplifier Gain Select *16 */
+#define SD16GAIN_32 (5<<3) /* AFE Input Pre-Amplifier Gain Select *32 */
+
+#define SD16INCH_0 (0<<0) /* SD16 Input Channel select input */
+#define SD16INCH_1 (1<<0) /* SD16 Input Channel select input */
+#define SD16INCH_2 (2<<0) /* SD16 Input Channel select input */
+#define SD16INCH_3 (3<<0) /* SD16 Input Channel select input */
+#define SD16INCH_4 (4<<0) /* SD16 Input Channel select input */
+#define SD16INCH_5 (5<<0) /* SD16 Input Channel select input */
+#define SD16INCH_6 (6<<0) /* SD16 Input Channel select Temp */
+#define SD16INCH_7 (7<<0) /* SD16 Input Channel select Offset */
+
+#define SD16INTDLY_0 (0<<6) /* SD16 Interrupt Delay: Int. after 4th conversion */
+#define SD16INTDLY_1 (1<<6) /* SD16 Interrupt Delay: Int. after 3rd conversion */
+#define SD16INTDLY_2 (2<<6) /* SD16 Interrupt Delay: Int. after 2nd conversion */
+#define SD16INTDLY_3 (3<<6) /* SD16 Interrupt Delay: Int. after 1st conversion */
+
+/* SD16CTL - AFECTL */
+#define SD16OVIE 0x0002 /* Overflow Interupt Enable */
+#define SD16REFON 0x0004 /* Switch internal Reference on */
+#define SD16VMIDON 0x0008 /* Switch Vmid Buffer on */
+#define SD16SSEL0 0x0010 /* SD16 Clock Source Select 0 */
+#define SD16SSEL1 0x0020 /* SD16 Clock Source Select 1 */
+#define SD16DIV0 0x0040 /* SD16 Clock Divider Select 0 */
+#define SD16DIV1 0x0080 /* SD16 Clock Divider Select 1 */
+#define SD16LP 0x0100 /* SD16 Low Power Mode Enable */
+#if defined(__MSP430_HAS_SD16_A__)
+#define SD16XDIV0 0x0200 /* SD16 2.Clock Divider Select 0 */
+#define SD16XDIV1 0x0400 /* SD16 2.Clock Divider Select 1 */
+//#define SD16XDIV2 0x0800) /* SD16 2.Clock Divider Select 2 */
+#endif
+
+#define SD16DIV_0 (0x0000) /* SD16 Clock Divider Select /1 */
+#define SD16DIV_1 (SD16DIV0) /* SD16 Clock Divider Select /2 */
+#define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */
+#define SD16DIV_3 (SD16DIV0|SD16DIV1) /* SD16 Clock Divider Select /8 */
+
+#if defined(__MSP430_HAS_SD16_A__)
+#define SD16XDIV_0 (0x0000) /* SD16 2.Clock Divider Select /1 */
+#define SD16XDIV_1 (SD16XDIV0) /* SD16 2.Clock Divider Select /3 */
+#define SD16XDIV_2 (SD16XDIV1) /* SD16 2.Clock Divider Select /16 */
+#define SD16XDIV_3 (SD16XDIV0|SD16XDIV1) /* SD16 2.Clock Divider Select /48 */
+#endif
+
+#define SD16SSEL_0 (0x0000) /* AFE Clock Source Select MCLK */
+#define SD16SSEL_1 (SD16SSEL0) /* AFE Clock Source Select SMCLK */
+#define SD16SSEL_2 (SD16SSEL1) /* AFE Clock Source Select ACLK */
+#define SD16SSEL_3 (SD16SSEL0|SD16SSEL1) /* AFE Clock Source Select TACLK */
+
+/* SD16CCTLx - AFECCTLx */
+#define SD16GRP 0x0001 /* Grouping of Channels: 0:Off/1:On */
+#define SD16SC 0x0002 /* Start Conversion */
+#define SD16IFG 0x0004 /* SD16 Channel x Interrupt Flag */
+#define SD16IE 0x0008 /* SD16 Channel x Interrupt Enable */
+#define SD16DF 0x0010 /* SD16 Channel x Data Format: 0:Unipolar/1:Bipolar */
+#define SD16OVIFG 0x0020 /* SD16 Channel x Overflow Interrupt Flag */
+#define SD16LSBACC 0x0040 /* SD16 Channel x Access LSB of ADC */
+#define SD16LSBTOG 0x0080 /* SD16 Channel x Toggle LSB Output of ADC */
+#define SD16OSR0 0x0100 /* SD16 Channel x OverSampling Ratio 0 */
+#define SD16OSR1 0x0200 /* SD16 Channel x OverSampling Ratio 1 */
+#define SD16SNGL 0x0400 /* SD16 Channel x Single Conversion On/Off */
+#if defined(__MSP430_HAS_SD16_A__)
+#define SD16XOSR 0x0800 /* SD16 Channel x Extended OverSampling Ratio */
+#define SD16UNI 0x1000 /* SD16 Channel x Bipolar(0) / Unipolar(1) Mode */
+#define SD16BUF0 0x2000 /* SD16 Channel x High Impedance Input Buffer Select: 0 */
+#define SD16BUF1 0x4000 /* SD16 Channel x High Impedance Input Buffer Select: 1 */
+#define SD16BUFG 0x8000 /* SD16 Channel x Buffer Gain 0:Gain=1 / 1:Gain=2 */
+#endif
+
+#if defined(__MSP430_HAS_SD16_A__)
+#define SD16OSR_1024 (SD16XOSR|SD16OSR0) /* SD16 Channel x OverSampling Ratio 1024 */
+#define SD16OSR_512 (SD16XOSR) /* SD16 Channel x OverSampling Ratio 512 */
+#endif
+#define SD16OSR_256 (0<<8) /* SD16 Channel x OverSampling Ratio 256 */
+#define SD16OSR_128 (1<<8) /* SD16 Channel x OverSampling Ratio 128 */
+#define SD16OSR_64 (2<<8) /* SD16 Channel x OverSampling Ratio 64 */
+#define SD16OSR_32 (3<<8) /* SD16 Channel x OverSampling Ratio 32 */
+
+#if defined(__MSP430_HAS_SD16_A__)
+#define SD16BUF_0 (0<<13) /* SD16 High Imp. Input Buffer: Disabled */
+#define SD16BUF_1 (1<<13) /* SD16 High Imp. Input Buffer: Slow */
+#define SD16BUF_2 (2<<13) /* SD16 High Imp. Input Buffer: Meduim */
+#define SD16BUF_3 (3<<13) /* SD16 High Imp. Input Buffer: Fast */
+#endif
+
+#if !defined(__MSP430_HAS_SD16_A__)
+#define AFEINCTL0 SD16INCTL0 /* SD16 Input Control Register Channel 0 */
+#define AFEINCTL1 SD16INCTL1 /* SD16 Input Control Register Channel 1 */
+#define AFEINCTL2 SD16INCTL2 /* SD16 Input Control Register Channel 2 */
+#define AFECTL SD16CTL /* SD16 Control Register */
+#define AFECCTL0 SD16CCTL0 /* SD16 Channel 0 Control Register */
+#define AFECCTL1 SD16CCTL1 /* SD16 Channel 1 Control Register */
+#define AFECCTL2 SD16CCTL02 /* SD16 Channel 2 Control Register */
+#endif
+
+
+/* Aliases by mspgcc */
+#define SD16DIV_DIV1 SD16DIV_0 /* SD16 Clock Divider Select /1 */
+#define SD16DIV_DIV2 SD16DIV_1 /* SD16 Clock Divider Select /2 */
+#define SD16DIV_DIV4 SD16DIV_2 /* SD16 Clock Divider Select /4 */
+#define SD16DIV_DIV8 SD16DIV_3 /* SD16 Clock Divider Select /8 */
+
+#if defined(__MSP430_HAS_SD16_A__)
+#define SD16XDIV_DIV1 SD16XDIV_0 /* SD16 2.Clock Divider Select /1 */
+#define SD16XDIV_DIV2 SD16XDIV_1 /* SD16 2.Clock Divider Select /3 */
+#define SD16XDIV_DIV4 SD16XDIV_2 /* SD16 2.Clock Divider Select /16 */
+#define SD16XDIV_DIV8 SD16XDIV_3 /* SD16 2.Clock Divider Select /48 */
+#endif
+
+#define SD16SSEL_MCLK SD16SSEL_0 /* AFE Clock Source Select MCLK */
+#define SD16SSEL_SMCLK SD16SSEL_1 /* AFE Clock Source Select SMCLK */
+#define SD16SSEL_ACLK SD16SSEL_2 /* AFE Clock Source Select ACLK */
+#define SD16SSEL_TACLK SD16SSEL_3 /* AFE Clock Source Select TACLK */
+
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_slopeadc_h
+#define __msp430_headers_slopeadc_h
+
+/* slopeadc.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Slope ADC header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: slopeadc.h,v 1.2 2002/12/28 06:52:18 coppice Exp $
+ */
+
+/* Switches: none */
+
+#define AIN_ 0x0110 /* ADC Input */
+sfrw(AIN,AIN_);
+#define AEN_ 0x0112 /* ADC Input Enable */
+sfrw(AEN,AEN_);
+
+#define ACTL_ 0x0114 /* ADC Control */
+sfrw(ACTL,ACTL_);
+/* the names of the mode bits are different from the spec */
+#define ADSOC 0x0001
+#define ADSVCC 0x0002
+#define ADIN0 0x0004
+#define ADIN1 0x0008
+#define ADIN2 0x0010
+#define ADINOFF 0x0020
+#define ADCSRC0 0x0040
+#define ADCSRC1 0x0080
+#define ADCSRCOFF 0x0100
+#define ADRNG0 0x0200
+#define ADRNG1 0x0400
+#define ADAUTO 0x0800
+#define ADPD 0x1000
+/* Channel select coded with Bits 2-5 */
+#define ADIN_A0 0 /* (default) */
+#define ADIN_A1 (ADIN0)
+#define ADIN_A2 (ADIN1)
+#define ADIN_A3 (ADIN1|ADIN0)
+#define ADIN_A4 (ADIN2)
+#define ADIN_A5 (ADIN2|ADIN0)
+#define ADIN_A6 (ADIN2|ADIN1)
+#define ADIN_A7 (ADIN2|ADIN1|ADIN0)
+/* Current source output select coded with Bits 6-8 */
+#define ADCSRC_A0 0 /* (default) */
+#define ADCSRC_A1 (ADCSRC0)
+#define ADCSRC_A2 (ADCSRC1)
+#define ADCSRC_A3 (ADCSRC1|ADCSRC0)
+/* Range select coded with Bits 9-11 */
+#define ADRNG_A 0 /* 0<=Vin<1/4Vref (default) */
+#define ADRNG_B (ADRNG0) /* 1/4 Vref<=Vin<1/2 Vref */
+#define ADRNG_C (ADRNG1) /* 1/2 Vref<=Vin<3/4 Vref */
+#define ADRNG_D (ADRNG1|ADRNG0) /* 3/4 Vref<=Vin<1 Vref */
+#define ADRNG_AUTO (ADAUTO) /* 0<=Vin<1 Vref auto detect range */
+
+/* DATA REGISTER ADDRESS */
+#define ADAT_ 0x0118 /* ADC Data */
+sfrw(ADAT,ADAT_);
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_svs_h
+#define __msp430_headers_svs_h
+
+/* svs.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Supply voltage supervisor
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: svs.h,v 1.6 2005/08/17 14:28:46 coppice Exp $
+ */
+
+/* Switches: __msp430_has_svs_at_0x55
+ __msp430_has_non_variable_svs_threshold */
+
+#if defined(__msp430_has_svs_at_0x55)
+#define SVSCTL_ 0x0055 /* SVS Control */
+#else
+#define SVSCTL_ 0x0056 /* SVS Control */
+#endif
+sfrb(SVSCTL,SVSCTL_);
+#define SVSFG 0x01
+#define SVSOP 0x02
+#define SVSON 0x04
+#define PORON 0x08
+#define VLDOFF 0x00
+#define VLDON 0x10
+#define VLD_1_8V 0x10
+
+/* Some additional defines to round out the definitions in the same style
+ as other peripherals. These are not in TI's header. */
+#define VLD0 (1<<4)
+#define VLD1 (2<<4)
+#define VLD2 (4<<4)
+#define VLD3 (8<<4)
+
+#if !defined(__msp430_has_non_variable_svs_threshold)
+#define VLD_OFF (0<<4)
+#define VLD_1 (1<<4)
+#define VLD_2 (2<<4)
+#define VLD_3 (3<<4)
+#define VLD_4 (4<<4)
+#define VLD_5 (5<<4)
+#define VLD_6 (6<<4)
+#define VLD_7 (7<<4)
+#define VLD_8 (8<<4)
+#define VLD_9 (9<<4)
+#define VLD_10 (10<<4)
+#define VLD_11 (11<<4)
+#define VLD_12 (12<<4)
+#define VLD_13 (13<<4)
+#define VLD_14 (14<<4)
+#define VLD_EXT (15<<4)
+#endif
+
+#endif
--- /dev/null
+#ifndef __MSP430_HEADERS_SYS_H
+#define __MSP430_HEADERS_SYS_H
+
+/* sys.h
+ *
+ * mspgcc project: MSP430 device headers
+ * system control module
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@users.sf.net>
+ * Originally based in MSP430F543x datasheet (slas609)
+ * and MSP430x5xx Family User's Guide (slau208).
+ *
+ * $Id: sys.h,v 1.3 2009/02/28 12:14:53 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_SYS_BASE__ - base address of SYS module
+
+*/
+
+#define SYSCTL_ __MSP430_SYS_BASE__ + 0x00 /* System control register */
+sfrw(SYSCTL, SYSCTL_);
+#define SYSCTL_L_ __MSP430_SYS_BASE__ + 0x00 /* low byte */
+sfrb(SYSCTL_L, SYSCTL_L_);
+#define SYSCTL_H_ __MSP430_SYS_BASE__ + 0x01 /* high byte */
+sfrb(SYSCTL_H, SYSCTL_H_);
+
+#define SYSBSLC_ __MSP430_SYS_BASE__ + 0x02 /* Bootstrap loader configuration register */
+sfrw(SYSBSLC, SYSBSLC_);
+#define SYSBSLC_L_ __MSP430_SYS_BASE__ + 0x02 /* low byte */
+sfrb(SYSBSLC_L, SYSBSLC_L_);
+#define SYSBSLC_H_ __MSP430_SYS_BASE__ + 0x03 /* high byte */
+sfrb(SYSBSLC_H, SYSBSLC_H_);
+
+#define SYSARB_ __MSP430_SYS_BASE__ + 0x04 /* Arbitration configuration register */
+sfrw(SYSARB, SYSARB_);
+#define SYSARB_L_ __MSP430_SYS_BASE__ + 0x04 /* low byte */
+sfrb(SYSARB_L, SYSARB_L_);
+#define SYSARB_H_ __MSP430_SYS_BASE__ + 0x05 /* high byte */
+sfrb(SYSARB_H, SYSARB_H_);
+
+#define SYSJMBC_ __MSP430_SYS_BASE__ + 0x06 /* JTAG Mailbox control register */
+sfrw(SYSJMBC, SYSJMBC_);
+#define SYSJMBC_L_ __MSP430_SYS_BASE__ + 0x06 /* low byte */
+sfrb(SYSJMBC_L, SYSJMBC_L_);
+#define SYSJMBC_H_ __MSP430_SYS_BASE__ + 0x07 /* high byte */
+sfrb(SYSJMBC_H, SYSJMBC_H_);
+
+#define SYSJMBI0_ __MSP430_SYS_BASE__ + 0x08 /* JTAG Mailbox input register #0 */
+sfrw(SYSJMBI0, SYSJMBI0_);
+#define SYSJMBI0_L_ __MSP430_SYS_BASE__ + 0x08 /* low byte */
+sfrb(SYSJMBI0_L, SYSJMBI0_L_);
+#define SYSJMBI0_H_ __MSP430_SYS_BASE__ + 0x09 /* high byte */
+sfrb(SYSJMBI0_H, SYSJMBI0_H_);
+
+#define SYSJMBI1_ __MSP430_SYS_BASE__ + 0x0A /* JTAG Mailbox input register #1 */
+sfrw(SYSJMBI1, SYSJMBI1_);
+#define SYSJMBI1_L_ __MSP430_SYS_BASE__ + 0x0A /* low byte */
+sfrb(SYSJMBI1_L, SYSJMBI1_L_);
+#define SYSJMBI1_H_ __MSP430_SYS_BASE__ + 0x0B /* high byte */
+sfrb(SYSJMBI1_H, SYSJMBI1_H_);
+
+#define SYSJMBO0_ __MSP430_SYS_BASE__ + 0x0C /* JTAG Mailbox output register #0 */
+sfrw(SYSJMBO0, SYSJMBO0_);
+#define SYSJMBO0_L_ __MSP430_SYS_BASE__ + 0x0C /* low byte */
+sfrb(SYSJMBO0_L, SYSJMBO0_L_);
+#define SYSJMBO0_H_ __MSP430_SYS_BASE__ + 0x0D /* high byte */
+sfrb(SYSJMBO0_H, SYSJMBO0_H_);
+
+#define SYSJMBO1_ __MSP430_SYS_BASE__ + 0x0E /* JTAG Mailbox output register #1 */
+sfrw(SYSJMBO1, SYSJMBO1_);
+#define SYSJMBO1_L_ __MSP430_SYS_BASE__ + 0x0E /* low byte */
+sfrb(SYSJMBO1_L, SYSJMBO1_L_);
+#define SYSJMBO1_H_ __MSP430_SYS_BASE__ + 0x0F /* high byte */
+sfrb(SYSJMBO1_H, SYSJMBO1_H_);
+
+#define SYSBERRIV_ __MSP430_SYS_BASE__ + 0x18 /* Bus error vector generator */
+sfrw(SYSBERRIV, SYSBERRIV_);
+#define SYSUNIV_ __MSP430_SYS_BASE__ + 0x1A /* User NMI vector generator */
+sfrw(SYSUNIV, SYSUNIV_);
+#define SYSSNIV_ __MSP430_SYS_BASE__ + 0x1C /* System NMI vector generator */
+sfrw(SYSSNIV, SYSSNIV_);
+#define SYSRSTIV_ __MSP430_SYS_BASE__ + 0x1E /* System reset vector generator */
+sfrw(SYSRSTIV, SYSRSTIV_);
+
+/* SYSCTL, SYSCTL_L */
+#define SYSJTAGPIN (1<<5) /* Dedicated JTAG pins enable */
+#define SYSBSLIND (1<<4) /* TCK/RST entry BSL indication detected */
+#define SYSPMMPE (1<<2) /* PMM access protect */
+#define SYSRIVECT (1<<0) /* RAM based interrupt vectors */
+
+/* SYSBSLC, SYSBSLC_L, SYSBSLC_H */
+#define SYSBSLPE (1<<15) /* BSL memory protection enable */
+#define SYSBSLOFF (1<<14) /* BSL memory disable for size covered in SYSBSLSIZE */
+#define SYSBSLR (1<<2) /* RAM assigned to BSL */
+#define SYSBSLSIZE1 (1<<1) /* BSL size */
+#define SYSBSLSIZE0 (1<<0) /* BSL size */
+
+#define SYSBSLSIZE_0 (0<<0) /* size 512 bytes, BSL_SEG_3 */
+#define SYSBSLSIZE_1 (1<<0) /* size 1024 bytes, BSL_SEG_2,3 */
+#define SYSBSLSIZE_2 (2<<0) /* size 1536 bytes, BSL_SEG_1,2,3 */
+#define SYSBSLSIZE_3 (3<<0) /* size 2048 bytes, BSL_SEG_0,1,2,3 */
+
+/* SYSJMBC, SYSJMBC_L */
+#define JMBCLR1OFF (1<<7) /* Incomming JTAG mailbox 1 flag auto-clear disable */
+#define MBCLR0OFF (1<<6) /* Incomming JTAG mailbox 0 flag auto-clear disable */
+#define JMBMODE (1<<4) /* Operation mode of JMB for JMBI0/1 and JMBO0/1 */
+#define JMBOUT1FG (1<<3) /* Outgoing JTAG mailbox 1 flag */
+#define JMBOUT0FG (1<<2) /* Outgoing JTAG mailbox 0 flag */
+#define JMBIN1FG (1<<1) /* Incoming JTAG mailbox 1 flag */
+#define JMBIN0FG (1<<0) /* Incoming JTAG mailbox 0 flag */
+
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+
+#undef __xstr
+#undef __str
+#define __xstr(x) __str(x)
+#define __str(x) #x
+
+typedef struct
+{
+ union
+ {
+ volatile unsigned int CTL; /* System control register */
+ struct
+ {
+ volatile unsigned char CTL_L; /* low byte */
+ volatile unsigned char CTL_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int BSLC; /* Bootstrap loader configuration register */
+ struct
+ {
+ volatile unsigned char BSLC_L; /* low byte */
+ volatile unsigned char BSLC_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int ARB; /* Arbitration configuration register */
+ struct
+ {
+ volatile unsigned char ARB_L; /* low byte */
+ volatile unsigned char ARB_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBC; /* JTAG Mailbox control register */
+ struct
+ {
+ volatile unsigned char JMBC_L; /* low byte */
+ volatile unsigned char JMBC_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBI0; /* JTAG Mailbox input register #0 */
+ struct
+ {
+ volatile unsigned char JMBI0_L; /* low byte */
+ volatile unsigned char JMBI0_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBI1; /* JTAG Mailbox input register #1 */
+ struct
+ {
+ volatile unsigned char JMBI1_L; /* low byte */
+ volatile unsigned char JMBI1_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBO0; /* JTAG Mailbox output register #0 */
+ struct
+ {
+ volatile unsigned char JMBO0_L; /* low byte */
+ volatile unsigned char JMBO0_H; /* high byte */
+ };
+ };
+ union
+ {
+ volatile unsigned int JMBO1; /* JTAG Mailbox output register #1 */
+ struct
+ {
+ volatile unsigned char JMBO1_L; /* low byte */
+ volatile unsigned char JMBO1_H; /* high byte */
+ };
+ };
+ unsigned int dummy[4];
+ volatile unsigned int BERRIV; /* Bus error vector generator */
+ volatile unsigned int UNIV; /* User NMI vector generator */
+ volatile unsigned int SNIV; /* System NMI vector generator */
+ volatile unsigned int RSTIV; /* System reset vector generator */
+} sys_t;
+sys_t SYS asm(__xstr(__MSP430_SYS_BASE__));
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __MSP430_HEADERS_SYS_H */
--- /dev/null
+#ifndef __msp430_headers_system_clock_h
+#define __msp430_headers_system_clock_h
+
+/* system_clock.h
+ *
+ * mspgcc project: MSP430 device headers
+ * SYSTEM_CLOCK module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: system_clock.h,v 1.7 2006/06/07 13:01:30 coppice Exp $
+ */
+
+/* Switches:
+
+__MSP430_HAS_FLL__ - if device has the original FLL
+__MSP430_HAS_FLLPLUS__ - if device has both an FLL+ and a Xtal oscillator 2
+__MSP430_HAS_FLLPLUS_SMALL__- if device has the smaller FLL+
+
+*/
+
+#define SCFI0_ 0x0050 /* System Clock Frequency Integrator 0 */
+sfrb(SCFI0,SCFI0_);
+#define FN_2 0x04
+#define FN_3 0x08
+#define FN_4 0x10
+#if defined(__MSP430_HAS_FLLPLUS__) || defined(__MSP430_HAS_FLLPLUS_SMALL__)
+#define FN_8 0x20 /* fDCOCLK = 10*fNominal */
+#define FLLD0 0x40 /* Loop Divider Bit : 0 */
+#define FLLD1 0x80 /* Loop Divider Bit : 1 */
+
+#define FLLD_1 0 /* Multiply Selected Loop Freq. By 1 */
+#define FLLD_2 (FLLD0) /* Multiply Selected Loop Freq. By 2 */
+#define FLLD_4 (FLLD1) /* Multiply Selected Loop Freq. By 4 */
+#define FLLD_8 (FLLD1|FLLD0) /* Multiply Selected Loop Freq. By 8 */
+#endif
+
+#define SCFI1_ 0x0051 /* System Clock Frequency Integrator 1 */
+sfrb(SCFI1,SCFI1_);
+#define SCFQCTL_ 0x0052 /* System Clock Frequency Control */
+sfrb(SCFQCTL,SCFQCTL_);
+/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
+/* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */
+/* #define SCFQ_64K 0x01 fMCLK=2*fACLK 3+1 to 127+1 is possible */
+#define SCFQ_128K 0x03 /* fMCLK=4*fACLK */
+#define SCFQ_256K 0x07 /* fMCLK=8*fACLK */
+#define SCFQ_512K 0x0F /* fMCLK=16*fACLK */
+#define SCFQ_1M 0x1F /* fMCLK=32*fACLK */
+#define SCFQ_2M 0x3F /* fMCLK=64*fACLK */
+#define SCFQ_4M 0x7F /* fMCLK=128*fACLK not possible for ICE */
+
+#if defined(__MSP430_HAS_FLLPLUS__) || defined(__MSP430_HAS_FLLPLUS_SMALL__)
+
+#define SCFQ_M 0x80 /* Modulation Disable */
+
+#define FLL_CTL0_ 0x0053 /* FLL+ Control 0 */
+sfrb(FLL_CTL0,FLL_CTL0_);
+#define DCOF 0x01 /* DCO Fault Flag */
+#define LFOF 0x02 /* Low Frequency Oscillator Fault Flag */
+#define XT1OF 0x04 /* High Frequency Oscillator Fault Flag */
+#if defined(__MSP430_HAS_FLLPLUS__)
+#define XT2OF 0x08 /* XT2 Oscillator Fault Flag */
+#endif
+#define XCAP0PF 0x00 /* XIN Cap = XOUT Cap = 0pf */
+#define XCAP10PF 0x10 /* XIN Cap = XOUT Cap = 10pf */
+#define XCAP14PF 0x20 /* XIN Cap = XOUT Cap = 14pf */
+#define XCAP18PF 0x30 /* XIN Cap = XOUT Cap = 18pf */
+#define XTS_FLL 0x40 /* 1: Selects high-freq. oscillator */
+#define DCOPLUS 0x80 /* DCO+ Enable */
+
+#define FLL_CTL1_ 0x0054 /* FLL+ Control 1 */
+sfrb(FLL_CTL1,FLL_CTL1_);
+#define FLL_DIV0 0x01 /* FLL+ Divide Px.x/ACLK 0 */
+#define FLL_DIV1 0x02 /* FLL+ Divide Px.x/ACLK 1 */
+
+#define FLL_DIV_1 0x00 /* FLL+ Divide Px.x/ACLK By 1 */
+#define FLL_DIV_2 0x01 /* FLL+ Divide Px.x/ACLK By 2 */
+#define FLL_DIV_4 0x02 /* FLL+ Divide Px.x/ACLK By 4 */
+#define FLL_DIV_8 0x03 /* FLL+ Divide Px.x/ACLK By 8 */
+
+#if defined(__MSP430_HAS_FLLPLUS__)
+#define SELS 0x04 /* Peripheral Module Clock Source (0: DCO, 1: XT2) */
+#define SELM0 0x08 /* MCLK Source Select 0 */
+#define SELM1 0x10 /* MCLK Source Select 1 */
+#define XT2OFF 0x20 /* High Frequency Oscillator 2 (XT2) disable */
+
+#define SELM_DCO 0x00 /* Select DCO for CPU MCLK */
+#define SELM_XT2 0x10 /* Select XT2 for CPU MCLK */
+#define SELM_A 0x18 /* Select A (from LFXT1) for CPU MCLK */
+#define SMCLKOFF 0x40 /* Peripheral Module Clock (SMCLK) disable */
+#endif
+
+#else
+
+#define CBCTL_ 0x0053 /* Crystal Buffer Control *** WRITE-ONLY *** */
+sfrb(CBCTL,CBCTL_);
+#define CBE 0x01
+#define CBSEL0 0x02
+#define CBSEL1 0x04
+/* Source select of frequency at output pin XBUF coded with Bits 1-2 in CBCTL */
+#define CBSEL_ACLK 0 /* source is ACLK (default after POR) */
+#define CBSEL_ACLK_DIV2 (CBSEL0) /* source is ACLK/2 */
+#define CBSEL_ACLK_DIV4 (CBSEL1) /* source is ACLK/4 */
+#define CBSEL_MCLK (CBSEL1|CBSEL0) /* source is MCLK */
+
+#endif
+
+/* INTERRUPT CONTROL BITS */
+/* These two bits are defined in the Special Function Registers */
+/* #define OFIFG 0x02 */
+/* #define OFIE 0x02 */
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_timer8_h
+#define __msp430_headers_timer8_h
+
+/* timer8.h
+ *
+ * mspgcc project: MSP430 device headers
+ * 8 bit timer
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: timer8.h,v 1.2 2002/12/28 06:51:02 coppice Exp $
+ */
+
+/* Switches: none */
+
+#define TCCTL_ 0x0042 /* Timer/Counter Control */
+sfrb(TCCTL,TCCTL_);
+/* The bit names have been prefixed with "TC" */
+#define TCRXD 0x01
+#define TCTXD 0x02
+#define TCRXACT 0x04
+#define TCENCNT 0x08
+#define TCTXE 0x10
+#define TCISCTL 0x20
+#define TCSSEL0 0x40
+#define TCSSEL1 0x80
+/* Source select of clock input coded with Bits 6-7 */
+#define TCSSEL_P01 0 /* source is signal at pin P0.1 (default) */
+#define TCSSEL_ACLK (TCSSEL0) /* source is ACLK */
+#define TCSSEL_MCLK (TCSSEL1) /* source is MCLK */
+#define TCSSEL_P01_MCLK (TCSSEL1|TCSSEL0) /* source is signal pin P0.1 .AND. MCLK */
+
+#define TCPLD 0x0043
+#define TCDAT 0x0044
+
+#endif
--- /dev/null
+#if !defined(__msp430_headers_timera_h__)
+#define __msp430_headers_timera_h__
+
+/* timera.h
+ *
+ * mspgcc project: MSP430 device headers
+ * TIMERA module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * 2009-05-19 - modifications by S. Balling <praktikum@innoventis.de>
+ * - added T0A5
+ * - added T1A3
+ *
+ * $Id: timera.h,v 1.15 2009/06/04 21:55:18 cliechti Exp $
+ */
+
+/* Switches:
+
+__MSP430_HAS_TA2__ - if the device has a timer0 A with 2 channels
+__MSP430_HAS_TA3__ - if the device has a timer0 A with 3 channels
+__MSP430_HAS_T1A2__ - if the device has a timer1 A with 2 channels, as well as timer0 A
+__MSP430_HAS_T1A5__ - if the device has a timer1 A with 5 channels, as well as timer0 A
+__MSP430_HAS_T0A5__ - if the device has a timer0 A with 5 channels
+__MSP430_HAS_T1A3__ - if the device has a timer1 A with 3 channels
+
+*/
+
+#if defined(__MSP430_HAS_T0A5__)
+#define TA0CTL_ 0x0340
+sfrw (TA0CTL,TA0CTL_);
+#define TA0CTL_L_ 0x0340
+sfrb (TA0CTL_L,TA0CTL_L_);
+#define TA0CTL_H_ 0x0341
+sfrb (TA0CTL_H,TA0CTL_H_);
+#define TA0CCTL0_ 0x0342
+sfrw (TA0CCTL0,TA0CCTL0_);
+#define TA0CCTL0_L_ 0x0342
+sfrb (TA0CCTL0_L,TA0CCTL0_L_);
+#define TA0CCTL0_H_ 0x0343
+sfrb (TA0CCTL0_H,TA0CCTL0_H_);
+#define TA0CCTL1_ 0x0344
+sfrw (TA0CCTL1,TA0CCTL1_);
+#define TA0CCTL1_L_ 0x0344
+sfrb (TA0CCTL1_L,TA0CCTL1_L_);
+#define TA0CCTL1_H_ 0x0345
+sfrb (TA0CCTL1_H,TA0CCTL1_H_);
+#define TA0CCTL2_ 0x0346
+sfrw (TA0CCTL2,TA0CCTL2_);
+#define TA0CCTL2_L_ 0x0346
+sfrb (TA0CCTL2_L,TA0CCTL2_L_);
+#define TA0CCTL2_H_ 0x0347
+sfrb (TA0CCTL2_H,TA0CCTL2_H_);
+#define TA0CCTL3_ 0x0348
+sfrw (TA0CCTL3,TA0CCTL3_);
+#define TA0CCTL3_L_ 0x0348
+sfrb (TA0CCTL3_L,TA0CCTL3_L_);
+#define TA0CCTL3_H_ 0x0349
+sfrb (TA0CCTL3_H,TA0CCTL3_H_);
+#define TA0CCTL4_ 0x034A
+sfrw (TA0CCTL4,TA0CCTL4_);
+#define TA0CCTL4_L_ 0x034A
+sfrb (TA0CCTL4_L,TA0CCTL4_L_);
+#define TA0CCTL4_H_ 0x034B
+sfrb (TA0CCTL4_H,TA0CCTL4_H_);
+#define TA0R_ 0x0350
+sfrw (TA0R,TA0R_);
+#define TA0R_L_ 0x0350
+sfrb (TA0R_L,TA0R_L_);
+#define TA0R_H_ 0x0351
+sfrb (TA0R_H,TA0R_H_);
+#define TA0CCR0_ 0x0352
+sfrw (TA0CCR0,TA0CCR0_);
+#define TA0CCR0_L_ 0x0352
+sfrb (TA0CCR0_L,TA0CCR0_L_);
+#define TA0CCR0_H_ 0x0353
+sfrb (TA0CCR0_H,TA0CCR0_H_);
+#define TA0CCR1_ 0x0354
+sfrw (TA0CCR1,TA0CCR1_);
+#define TA0CCR1_L_ 0x0354
+sfrb (TA0CCR1_L,TA0CCR1_L_);
+#define TA0CCR1_H_ 0x0355
+sfrb (TA0CCR1_H,TA0CCR1_H_);
+#define TA0CCR2_ 0x0356
+sfrw (TA0CCR2,TA0CCR2_);
+#define TA0CCR2_L_ 0x0356
+sfrb (TA0CCR2_L,TA0CCR2_L_);
+#define TA0CCR2_H_ 0x0357
+sfrb (TA0CCR2_H,TA0CCR2_H_);
+#define TA0CCR3_ 0x0358
+sfrw (TA0CCR3,TA0CCR3_);
+#define TA0CCR3_L_ 0x0358
+sfrb (TA0CCR3_L,TA0CCR3_L_);
+#define TA0CCR3_H_ 0x0359
+sfrb (TA0CCR3_H,TA0CCR3_H_);
+#define TA0CCR4_ 0x035A
+sfrw (TA0CCR4,TA0CCR4_);
+#define TA0CCR4_L_ 0x035A
+sfrb (TA0CCR4_L,TA0CCR4_L_);
+#define TA0CCR4_H_ 0x035B
+sfrb (TA0CCR4_H,TA0CCR4_H_);
+#define TA0IV_ 0x036E
+sfrw (TA0IV,TA0IV_);
+#define TA0IV_L_ 0x036E
+sfrb (TA0IV_L,TA0IV_L_);
+#define TA0IV_H_ 0x036F
+sfrb (TA0IV_H,TA0IV_H_);
+#define TA0EX0_ 0x0360
+sfrw (TA0EX0,TA0EX0_);
+#define TA0EX0_L_ 0x0360
+sfrb (TA0EX0_L,TA0EX0_L_);
+#define TA0EX0_H_ 0x0361
+sfrb (TA0EX0_H,TA0EX0_H_);
+#endif /* __MSP430_HAS_T0A5__ */
+
+#if defined(__MSP430_HAS_T1A3__)
+#define TA1CTL_ 0x0380
+sfrw (TA1CTL,TA1CTL_);
+#define TA1CTL_L_ 0x0380
+sfrb (TA1CTL_L,TA1CTL_L_);
+#define TA1CTL_H_ 0x0381
+sfrb (TA1CTL_H,TA1CTL_H_);
+#define TA1CCTL0_ 0x0382
+sfrw (TA1CCTL0,TA1CCTL0_);
+#define TA1CCTL0_L_ 0x0382
+sfrb (TA1CCTL0_L,TA1CCTL0_L_);
+#define TA1CCTL0_H_ 0x0383
+sfrb (TA1CCTL0_H,TA1CCTL0_H_);
+#define TA1CCTL1_ 0x0384
+sfrw (TA1CCTL1,TA1CCTL1_);
+#define TA1CCTL1_L_ 0x0384
+sfrb (TA1CCTL1_L,TA1CCTL1_L_);
+#define TA1CCTL1_H_ 0x0385
+sfrb (TA1CCTL1_H,TA1CCTL1_H_);
+#define TA1CCTL2_ 0x0386
+sfrw (TA1CCTL2,TA1CCTL2_);
+#define TA1CCTL2_L_ 0x0386
+sfrb (TA1CCTL2_L,TA1CCTL2_L_);
+#define TA1CCTL2_H_ 0x0387
+sfrb (TA1CCTL2_H,TA1CCTL2_H_);
+#define TA1R_ 0x0390
+sfrw (TA1R,TA1R_);
+#define TA1R_L_ 0x0390
+sfrb (TA1R_L,TA1R_L_);
+#define TA1R_H_ 0x0391
+sfrb (TA1R_H,TA1R_H_);
+#define TA1CCR0_ 0x0392
+sfrw (TA1CCR0,TA1CCR0_);
+#define TA1CCR0_L_ 0x0392
+sfrb (TA1CCR0_L,TA1CCR0_L_);
+#define TA1CCR0_H_ 0x0393
+sfrb (TA1CCR0_H,TA1CCR0_H_);
+#define TA1CCR1_ 0x0394
+sfrw (TA1CCR1,TA1CCR1_);
+#define TA1CCR1_L_ 0x0394
+sfrb (TA1CCR1_L,TA1CCR1_L_);
+#define TA1CCR1_H_ 0x0395
+sfrb (TA1CCR1_H,TA1CCR1_H_);
+#define TA1CCR2_ 0x0396
+sfrw (TA1CCR2,TA1CCR2_);
+#define TA1CCR2_L_ 0x0396
+sfrb (TA1CCR2_L,TA1CCR2_L_);
+#define TA1CCR2_H_ 0x0397
+sfrb (TA1CCR2_H,TA1CCR2_H_);
+#define TA1IV_ 0x03AE
+sfrw (TA1IV,TA1IV_);
+#define TA1IV_L_ 0x03AE
+sfrb (TA1IV_L,TA1IV_L_);
+#define TA1IV_H_ 0x03AF
+sfrb (TA1IV_H,TA1IV_H_);
+#define TA1EX0_ 0x03A0
+sfrw (TA1EX0,TA1EX0_);
+#define TA1EX0_L_ 0x03A0
+sfrb (TA1EX0_L,TA1EX0_L_);
+#define TA1EX0_H_ 0x03A1
+sfrb (TA1EX0_H,TA1EX0_H_);
+#endif /* __MSP430_HAS_T1A3__ */
+
+#if defined(__MSP430_HAS_TA2__) || defined(__MSP430_HAS_TA3__)
+#define TA0IV_ 0x012E /* Timer A 0 Interrupt Vector Word */
+sfrw (TA0IV,TA0IV_);
+#define TA0CTL_ 0x0160 /* Timer A 0 Control */
+sfrw (TA0CTL,TA0CTL_);
+#define TA0R_ 0x0170 /* Timer A 0 */
+sfrw (TA0R,TA0R_);
+
+#define TA0CCTL0_ 0x0162 /* Timer A 0 Capture/Compare Control 0 */
+sfrw (TA0CCTL0,TA0CCTL0_);
+#define TA0CCTL1_ 0x0164 /* Timer A 0 Capture/Compare Control 1 */
+sfrw (TA0CCTL1,TA0CCTL1_);
+#define TA0CCR0_ 0x0172 /* Timer A 0 Capture/Compare 0 */
+sfrw (TA0CCR0,TA0CCR0_);
+#define TA0CCR1_ 0x0174 /* Timer A 0 Capture/Compare 1 */
+sfrw (TA0CCR1,TA0CCR1_);
+
+/* Alternate register names */
+#define TAIV TA0IV
+#define TAIV_ TA0IV_
+#define TACTL TA0CTL
+#define TACTL_ TA0CTL_
+#define TAR TA0R
+#define TAR_ TA0R_
+
+#define TACCTL0 TA0CCTL0
+#define TACCTL0_ TA0CCTL0_
+#define TACCTL1 TA0CCTL1
+#define TACCTL1_ TA0CCTL1_
+#define TACCR0 TA0CCR0
+#define TACCR0_ TA0CCR0_
+#define TACCR1 TA0CCR1
+#define TACCR1_ TA0CCR1_
+
+/* Further alternate register names */
+#define CCTL0 TA0CCTL0
+#define CCTL0_ TA0CCTL0_
+#define CCTL1 TA0CCTL1
+#define CCTL1_ TA0CCTL1_
+#define CCR0 TA0CCR0
+#define CCR0_ TA0CCR0_
+#define CCR1 TA0CCR1
+#define CCR1_ TA0CCR1_
+#endif
+
+#if defined(__MSP430_HAS_TA3__)
+#define TA0CCTL2_ 0x0166 /* Timer A 0 Capture/Compare Control 2 */
+sfrw (TA0CCTL2,TA0CCTL2_);
+#define TA0CCR2_ 0x0176 /* Timer A 0 Capture/Compare 2 */
+sfrw (TA0CCR2,TA0CCR2_);
+
+/* Alternate register names */
+#define TACCTL2 TA0CCTL2
+#define TACCTL2_ TA0CCTL2_
+#define TACCR2 TA0CCR2
+#define TACCR2_ TA0CCR2_
+
+/* Further alternate register names */
+#define CCTL2 TA0CCTL2
+#define CCTL2_ TA0CCTL2_
+#define CCR2 TA0CCR2
+#define CCR2_ TA0CCR2_
+#endif
+
+#if defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T1A5__)
+#define TA1IV_ 0x011E /* Timer A 1 Interrupt Vector Word */
+sfrw (TA1IV, TA1IV_);
+#define TA1CTL_ 0x0180 /* Timer A 1 Control */
+sfrw (TA1CTL, TA1CTL_);
+#define TA1CCTL0_ 0x0182 /* Timer A 1 Capture/Compare Control 0 */
+sfrw (TA1CCTL0, TA1CCTL0_);
+#define TA1CCTL1_ 0x0184 /* Timer A 1 Capture/Compare Control 1 */
+sfrw (TA1CCTL1, TA1CCTL1_);
+#if defined(__MSP430_HAS_T1A5__)
+#define TA1CCTL2_ 0x0186 /* Timer A 1 Capture/Compare Control 2 */
+sfrw (TA1CCTL2, TA1CCTL2_);
+#define TA1CCTL3_ 0x0188 /* Timer A 1 Capture/Compare Control 3 */
+sfrw (TA1CCTL3, TA1CCTL3_);
+#define TA1CCTL4_ 0x018A /* Timer A 1 Capture/Compare Control 4 */
+sfrw (TA1CCTL4, TA1CCTL4_);
+#endif
+#define TAR1_ 0x0190 /* Timer A 1 */
+sfrw (TAR1, TAR1_);
+#define TA1CCR0_ 0x0192 /* Timer A 1 Capture/Compare 0 */
+sfrw (TA1CCR0, TA1CCR0_);
+#define TA1CCR1_ 0x0194 /* Timer A 1 Capture/Compare 1 */
+sfrw (TA1CCR1, TA1CCR1_);
+#if defined(__MSP430_HAS_T1A5__)
+#define TA1CCR2_ 0x0196 /* Timer A 1 Capture/Compare 2 */
+sfrw (TA1CCR2, TA1CCR2_);
+#define TA1CCR3_ 0x0198 /* Timer A 1 Capture/Compare 3 */
+sfrw (TA1CCR3, TA1CCR3_);
+#define TA1CCR4_ 0x019A /* Timer A 1 Capture/Compare 4 */
+sfrw (TA1CCR4, TA1CCR4_);
+#endif
+#endif
+
+#if !defined(__ASSEMBLER__)
+/* Structured declaration */
+typedef struct {
+ volatile unsigned
+ taifg:1,
+ taie:1,
+ taclr:1,
+ dummy:1,
+ tamc:2,
+ taid:2,
+ tassel:2;
+} __attribute__ ((packed)) tactl_t;
+
+typedef struct {
+ volatile unsigned
+ ccifg:1,
+ cov:1,
+ out:1,
+ cci:1,
+ ccie:1,
+ outmod:3,
+ cap:1,
+ dummy:1,
+ scci:1,
+ scs:1,
+ ccis:2,
+ cm:2;
+} __attribute__ ((packed)) tacctl_t;
+
+#if defined(__MSP430_HAS_TA2__) || defined(__MSP430_HAS_TA3__)
+/* The timer A declaration itself */
+struct timera_t {
+ tactl_t ctl;
+ tacctl_t cctl0;
+ tacctl_t cctl1;
+#if defined(__MSP430_HAS_TA3__)
+ tacctl_t cctl2;
+#else
+ volatile unsigned dummy1[1]; /* Pad to the next group of registers */
+#endif
+ volatile unsigned dummy2[4]; /* Pad to the next group of registers */
+ volatile unsigned tar;
+ volatile unsigned taccr0;
+ volatile unsigned taccr1;
+#if defined(__MSP430_HAS_TA3__)
+ volatile unsigned taccr2;
+#endif
+};
+#ifdef __cplusplus
+extern "C" struct timera_t timera asm("0x0160");
+#else //__cplusplus
+struct timera_t timera asm("0x0160");
+#endif //__cplusplus
+#endif // __MSP430_HAS_TA2__ || __MSP430_HAS_TA3__
+
+#if defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T1A5__)
+/* The timer A1 declaration itself */
+struct timera1_t {
+ tactl_t ctl;
+ tacctl_t cctl0;
+ tacctl_t cctl1;
+#if defined(__MSP430_HAS_T1A5__)
+ tacctl_t cctl2;
+ tacctl_t cctl3;
+ tacctl_t cctl4;
+#else
+ volatile unsigned dummy1[3]; /* Pad to the next group of registers */
+#endif
+ volatile unsigned dummy2[2]; /* Pad to the next group of registers */
+ volatile unsigned tar;
+ volatile unsigned taccr0;
+ volatile unsigned taccr1;
+#if defined(__MSP430_HAS_T1A5__)
+ volatile unsigned taccr2;
+ volatile unsigned taccr3;
+ volatile unsigned taccr4;
+#endif
+};
+#ifdef __cplusplus
+extern "C" struct timera1_t timera1 asm("0x0180");
+#else //__cplusplus
+struct timera1_t timera1 asm("0x0180");
+#endif //__cplusplus
+
+#endif
+#endif
+
+#define TASSEL2 0x0400 /* unused */ /* to distinguish from UART SSELx */
+#define TASSEL1 0x0200 /* Timer A clock source select 1 */
+#define TASSEL0 0x0100 /* Timer A clock source select 0 */
+#define ID1 0x0080 /* Timer A clock input divider 1 */
+#define ID0 0x0040 /* Timer A clock input divider 0 */
+#define MC1 0x0020 /* Timer A mode control 1 */
+#define MC0 0x0010 /* Timer A mode control 0 */
+#define TACLR 0x0004 /* Timer A counter clear */
+#define TAIE 0x0002 /* Timer A counter interrupt enable */
+#define TAIFG 0x0001 /* Timer A counter interrupt flag */
+
+#define MC_0 (0<<4) /* Timer A mode control: 0 - Stop */
+#define MC_1 (1<<4) /* Timer A mode control: 1 - Up to CCR0 */
+#define MC_2 (2<<4) /* Timer A mode control: 2 - Continous up */
+#define MC_3 (3<<4) /* Timer A mode control: 3 - Up/Down */
+#define ID_0 (0<<6) /* Timer A input divider: 0 - /1 */
+#define ID_1 (1<<6) /* Timer A input divider: 1 - /2 */
+#define ID_2 (2<<6) /* Timer A input divider: 2 - /4 */
+#define ID_3 (3<<6) /* Timer A input divider: 3 - /8 */
+#define TASSEL_0 (0<<8) /* Timer A clock source select: 0 - TACLK */
+#define TASSEL_1 (1<<8) /* Timer A clock source select: 1 - ACLK */
+#define TASSEL_2 (2<<8) /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL_3 (3<<8) /* Timer A clock source select: 3 - INCLK */
+
+#define CM1 0x8000 /* Capture mode 1 */
+#define CM0 0x4000 /* Capture mode 0 */
+#define CCIS1 0x2000 /* Capture input select 1 */
+#define CCIS0 0x1000 /* Capture input select 0 */
+#define SCS 0x0800 /* Capture sychronize */
+#define SCCI 0x0400 /* Latched capture signal (read) */
+#define CAP 0x0100 /* Capture mode: 1 /Compare mode : 0 */
+#define OUTMOD2 0x0080 /* Output mode 2 */
+#define OUTMOD1 0x0040 /* Output mode 1 */
+#define OUTMOD0 0x0020 /* Output mode 0 */
+#define CCIE 0x0010 /* Capture/compare interrupt enable */
+#define CCI 0x0008 /* Capture input signal (read) */
+#define OUT 0x0004 /* PWM Output signal if output mode 0 */
+#define COV 0x0002 /* Capture/compare overflow flag */
+#define CCIFG 0x0001 /* Capture/compare interrupt flag */
+
+#define OUTMOD_0 (0<<5) /* PWM output mode: 0 - output only */
+#define OUTMOD_1 (1<<5) /* PWM output mode: 1 - set */
+#define OUTMOD_2 (2<<5) /* PWM output mode: 2 - PWM toggle/reset */
+#define OUTMOD_3 (3<<5) /* PWM output mode: 3 - PWM set/reset */
+#define OUTMOD_4 (4<<5) /* PWM output mode: 4 - toggle */
+#define OUTMOD_5 (5<<5) /* PWM output mode: 5 - Reset */
+#define OUTMOD_6 (6<<5) /* PWM output mode: 6 - PWM toggle/set */
+#define OUTMOD_7 (7<<5) /* PWM output mode: 7 - PWM reset/set */
+#define CCIS_0 (0<<12) /* Capture input select: 0 - CCIxA */
+#define CCIS_1 (1<<12) /* Capture input select: 1 - CCIxB */
+#define CCIS_2 (2<<12) /* Capture input select: 2 - GND */
+#define CCIS_3 (3<<12) /* Capture input select: 3 - Vcc */
+#define CM_0 (0<<14) /* Capture mode: 0 - disabled */
+#define CM_1 (1<<14) /* Capture mode: 1 - pos. edge */
+#define CM_2 (2<<14) /* Capture mode: 1 - neg. edge */
+#define CM_3 (3<<14) /* Capture mode: 1 - both edges */
+
+/* Aliases by mspgcc */
+#define MC_STOP MC_0
+#define MC_UPTO_CCR0 MC_1
+#define MC_CONT MC_2
+#define MC_UPDOWN MC_3
+
+#define ID_DIV1 ID_0
+#define ID_DIV2 ID_1
+#define ID_DIV4 ID_2
+#define ID_DIV8 ID_3
+
+#define TASSEL_TACLK TASSEL_0
+#define TASSEL_ACLK TASSEL_1
+#define TASSEL_SMCLK TASSEL_2
+#define TASSEL_INCLK TASSEL_3
+
+#define OUTMOD_OUT OUTMOD_0
+#define OUTMOD_SET OUTMOD_1
+#define OUTMOD_TOGGLE_RESET OUTMOD_2
+#define OUTMOD_SET_RESET OUTMOD_3
+#define OUTMOD_TOGGLE OUTMOD_4
+#define OUTMOD_RESET OUTMOD_5
+#define OUTMOD_TOGGLE_SET OUTMOD_6
+#define OUTMOD_RESET_SET OUTMOD_7
+
+#define CM_DISABLE CM_0
+#define CM_POS CM_1
+#define CM_NEG CM_2
+#define CM_BOTH CM_3
+
+/* TimerA IV names */
+#if defined(__MSP430_HAS_TA3__) || defined(__MSP430_HAS_TA2____)
+ #define TAIV_NONE 0x00 /* No interrupt pending */
+ #define TAIV_CCR1 0x02 /* Capture/compare 1 TACCR1 CCIFG Highest */
+ #if defined(__MSP430_HAS_TA3__)
+ #define TAIV_CCR2 0x04 /* Capture/compare 2 TACCR2 CCIFG */
+ #endif /*__MSP430_HAS_TA3__*/
+ #define TAIV_OVERFLOW 0x0A /* Timer overflow TAIFG Lowest */
+#endif /*__MSP430_HAS_TA3__ || __MSP430_HAS_TA2__*/
+
+#endif
--- /dev/null
+#if !defined(__msp430_headers_timerb_h__)
+#define __msp430_headers_timerb_h__
+
+/* timerb.h
+ *
+ * mspgcc project: MSP430 device headers
+ * TIMERB module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: timerb.h,v 1.12 2008/10/09 15:00:14 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_HAS_TB7__ - if timer B has 7 capture/compare registers (default is 3)
+
+*/
+
+#define TBIV_ 0x011E /* Timer B Interrupt Vector Word */
+sfrw(TBIV,TBIV_);
+#define TBCTL_ 0x0180 /* Timer B Control */
+sfrw(TBCTL,TBCTL_);
+#define TBR_ 0x0190 /* Timer B */
+sfrw(TBR,TBR_);
+
+#define TBCCTL0_ 0x0182 /* Timer B Capture/Compare Control 0 */
+sfrw(TBCCTL0,TBCCTL0_);
+#define TBCCTL1_ 0x0184 /* Timer B Capture/Compare Control 1 */
+sfrw(TBCCTL1,TBCCTL1_);
+#define TBCCTL2_ 0x0186 /* Timer B Capture/Compare Control 2 */
+sfrw(TBCCTL2,TBCCTL2_);
+#define TBCCR0_ 0x0192 /* Timer B Capture/Compare 0 */
+sfrw(TBCCR0,TBCCR0_);
+#define TBCCR1_ 0x0194 /* Timer B Capture/Compare 1 */
+sfrw(TBCCR1,TBCCR1_);
+#define TBCCR2_ 0x0196 /* Timer B Capture/Compare 2 */
+sfrw(TBCCR2,TBCCR2_);
+
+#if defined(__MSP430_HAS_TB7__)
+
+#define TBCCTL3_ 0x0188 /* Timer B Capture/Compare Control 3 */
+sfrw(TBCCTL3,TBCCTL3_);
+#define TBCCTL4_ 0x018A /* Timer B Capture/Compare Control 4 */
+sfrw(TBCCTL4,TBCCTL4_);
+#define TBCCTL5_ 0x018C /* Timer B Capture/Compare Control 5 */
+sfrw(TBCCTL5,TBCCTL5_);
+#define TBCCTL6_ 0x018E /* Timer B Capture/Compare Control 6 */
+sfrw(TBCCTL6,TBCCTL6_);
+#define TBCCR3_ 0x0198 /* Timer B Capture/Compare 3 */
+sfrw(TBCCR3,TBCCR3_);
+#define TBCCR4_ 0x019A /* Timer B Capture/Compare 4 */
+sfrw(TBCCR4,TBCCR4_);
+#define TBCCR5_ 0x019C /* Timer B Capture/Compare 5 */
+sfrw(TBCCR5,TBCCR5_);
+#define TBCCR6_ 0x019E /* Timer B Capture/Compare 6 */
+sfrw(TBCCR6,TBCCR6_);
+
+#endif
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+typedef struct {
+ volatile unsigned
+ tbifg:1,
+ tbie:1,
+ tbclr:1,
+ dummy1:1,
+ tbmc:2,
+ tbid:2,
+ tbssel:2,
+ dummy2:1,
+ tbcntl:2,
+ tbclgrp:2;
+} __attribute__ ((packed)) tbctl_t;
+
+typedef struct {
+ volatile unsigned
+ ccifg:1,
+ cov:1,
+ out:1,
+ cci:1,
+ ccie:1,
+ outmod:3,
+ cap:1,
+ clld:2,
+ scs:1,
+ ccis:2,
+ cm:2;
+} __attribute__ ((packed)) tbcctl_t;
+
+/* The timer B declaration itself */
+struct timerb_t {
+ tbctl_t ctl;
+ tbcctl_t cctl0;
+ tbcctl_t cctl1;
+ tbcctl_t cctl2;
+#if defined(__MSP430_HAS_TB7__)
+ tbcctl_t cctl3;
+ tbcctl_t cctl4;
+ tbcctl_t cctl5;
+ tbcctl_t cctl6;
+#else
+ volatile unsigned dummy[4]; /* Pad to the next group of registers */
+#endif
+ volatile unsigned tbr;
+ volatile unsigned tbccr0;
+ volatile unsigned tbccr1;
+ volatile unsigned tbccr2;
+#if defined(__MSP430_HAS_TB7__)
+ volatile unsigned tbccr3;
+ volatile unsigned tbccr4;
+ volatile unsigned tbccr5;
+ volatile unsigned tbccr6;
+#endif
+};
+
+#ifdef __cplusplus
+extern "C" struct timerb_t timerb asm("0x0180");
+#else //__cplusplus
+struct timerb_t timerb asm("0x0180");
+#endif //__cplusplus
+
+#endif
+
+#define SHR1 0x4000 /* Timer B compare latch load group 1 */
+#define SHR0 0x2000 /* Timer B compare latch load group 0 */
+#define TBCLGRP1 0x4000 /* Timer B compare latch load group 1 */
+#define TBCLGRP0 0x2000 /* Timer B compare latch load group 0 */
+#define CNTL1 0x1000 /* Counter length 1 */
+#define CNTL0 0x0800 /* Counter length 0 */
+#define TBSSEL2 0x0400 /* unused */
+#define TBSSEL1 0x0200 /* Clock source 1 */
+#define TBSSEL0 0x0100 /* Clock source 0 */
+#define TBCLR 0x0004 /* Timer B counter clear */
+#define TBIE 0x0002 /* Timer B interrupt enable */
+#define TBIFG 0x0001 /* Timer B interrupt flag */
+
+#define TBSSEL_0 (0<<8) /* Clock source: TBCLK */
+#define TBSSEL_1 (1<<8) /* Clock source: ACLK */
+#define TBSSEL_2 (2<<8) /* Clock source: SMCLK */
+#define TBSSEL_3 (3<<8) /* Clock source: INCLK */
+#define CNTL_0 (0<<11) /* Counter length: 16 bit */
+#define CNTL_1 (1<<11) /* Counter length: 12 bit */
+#define CNTL_2 (2<<11) /* Counter length: 10 bit */
+#define CNTL_3 (3<<11) /* Counter length: 8 bit */
+#define SHR_0 (0<<13) /* Timer B Group: 0 - individually */
+#define SHR_1 (1<<13) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define SHR_2 (2<<13) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
+#define SHR_3 (3<<13) /* Timer B Group: 3 - 1 group (all) */
+#define TBCLGRP_0 (0<<13) /* Timer B Group: 0 - individually */
+#define TBCLGRP_1 (1<<13) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define TBCLGRP_2 (2<<13) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
+#define TBCLGRP_3 (3<<13) /* Timer B Group: 3 - 1 group (all) */
+
+/* Additional Timer B Control Register bits are defined in Timer A */
+
+#define SLSHR1 0x0400 /* Compare latch load source 1 */
+#define SLSHR0 0x0200 /* Compare latch load source 0 */
+#define CLLD1 0x0400 /* Compare latch load source 1 */
+#define CLLD0 0x0200 /* Compare latch load source 0 */
+
+#define SLSHR_0 (0<<9) /* Compare latch load source 0 - immediate */
+#define SLSHR_1 (1<<9) /* Compare latch load source 1 - TBR counts to 0 */
+#define SLSHR_2 (2<<9) /* Compare latch load source 2 - up/down */
+#define SLSHR_3 (3<<9) /* Compare latch load source 3 - TBR counts to TBCTL0 */
+
+#define CLLD_0 (0<<9) /* Compare latch load source 0 - immediate */
+#define CLLD_1 (1<<9) /* Compare latch load source 1 - TBR counts to 0 */
+#define CLLD_2 (2<<9) /* Compare latch load source 2 - up/down */
+#define CLLD_3 (3<<9) /* Compare latch load source 3 - TBR counts to TBCTL0 */
+
+/* Aliases by mspgcc */
+#define TBSSEL_TBCLK TBSSEL_0
+#define TBSSEL_ACLK TBSSEL_1
+#define TBSSEL_SMCLK TBSSEL_2
+#define TBSSEL_INCLK TBSSEL_3
+
+/* TimerB IV names */
+#define TBIV_NONE 0x00 /* No interrupt pending */
+#define TBIV_CCR1 0x02 /* Capture/compare 1 TBCCR1 CCIFG Highest */
+#define TBIV_CCR2 0x04 /* Capture/compare 2 TBCCR2 CCIFG */
+#if defined(__MSP430_HAS_TB7__)
+ #define TBIV_CCR3 0x06 /* Capture/compare 3 TBCCR3 CCIFG */
+ #define TBIV_CCR4 0x08 /* Capture/compare 4 TBCCR4 CCIFG */
+ #define TBIV_CCR5 0x0A /* Capture/compare 5 TBCCR5 CCIFG */
+ #define TBIV_CCR6 0x0C /* Capture/compare 6 TBCCR6 CCIFG */
+#endif /*__MSP430_HAS_TB7__B7*/
+#define TBIV_OVERFLOW 0x0E /* Timer overflow TBIFG Lowest */
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_timerport_h
+#define __msp430_headers_timerport_h
+
+/* timerport.h
+ *
+ * mspgcc project: MSP430 device headers
+ * Timer / IO port module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: timerport.h,v 1.2 2002/12/28 06:50:18 coppice Exp $
+ */
+
+/* Switches: none */
+
+#define TPCTL_ 0x004B /* Timer/Port Control */
+sfrb(TPCTL,TPCTL_);
+#define EN1FG 0x01
+#define RC1FG 0x02
+#define RC2FG 0x04
+#define EN1 0x08
+#define ENA 0x10
+#define ENB 0x20
+#define TPSSEL0 0x40
+#define TPSSEL1 0x80
+/* The EN1 signal of TPCNT1 is coded with with Bits 3-5 in TPCTL */
+#define TPCNT1_EN_OFF 0 /* TPCNT1 is disabled */
+#define TPCNT1_EN_ON ENA /* " is enabled */
+#define TPCNT1_EN_nTPIN5 ENB /* " is enabled with ~TPIN.5 */
+#define TPCNT1_EN_TPIN5 (TPSSEL0|ENB) /* " is enabled with TPIN.5 */
+#define TPCNT1_EN_nCIN (ENB|ENA) /* " is enabled with ~CIN */
+#define TPCNT1_EN_CIN (TPSSEL0|ENB|ENA) /* " is enabled with CIN */
+
+/* Source select of clock input coded with Bits 6-7 in TPCTL */
+#define TPSSEL_CLK1_CIN 0 /* CLK1 source is signal at CIN (default) */
+#define TPSSEL_CLK1_ACLK TPSSEL0 /* CLK1 source is ACLK */
+#define TPSSEL_CLK1_MCLK TPSSEL1 /* CLK1 source is MCLK */
+
+/* DATA REGISTER ADDRESSES */
+#define TPCNT1_ 0x004C /* Timer/Port Counter 1 */
+sfrb(TPCNT1,TPCNT1_);
+#define TPCNT2_ 0x004D /* Timer/Port Counter 2 */
+sfrb(TPCNT2,TPCNT2_);
+
+#define TPD_ 0x004E /* Timer/Port Data */
+sfrb(TPD,TPD_);
+#define TPD_0 0x01
+#define TPD_1 0x02
+#define TPD_2 0x04
+#define TPD_3 0x08
+#define TPD_4 0x10
+#define TPD_5 0x20
+#define CPON 0x40
+#define B16 0x80
+
+#define TPE_ 0x004F /* Timer/Port Enable */
+sfrb(TPE,TPE_);
+#define TPE_0 0x01
+#define TPE_1 0x02
+#define TPE_2 0x04
+#define TPE_3 0x08
+#define TPE_4 0x10
+#define TPE_5 0x20
+#define TPSSEL2 0x40
+#define TPSSEL3 0x80
+/* Source select of clock input coded with Bits 6-7 in TPE
+ NOTE: If the control bit B16 in TPD is set, TPSSEL2/3
+ are 'don't care' and the clock source of counter
+ TPCNT2 is the same as of the counter TPCNT1. */
+#define TPSSEL_CLK2_TPIN5 0 /* CLK2 source is signal TPIN.5 (default) */
+#define TPSSEL_CLK2_ACLK TPSSEL2 /* CLK2 source is ACLK */
+#define TPSSEL_CLK2_MCLK TPSSEL3 /* CLK2 source is MCLK */
+#define TPSSEL_CLK2_OFF (TPSSEL3|TPSSEL2) /* CLK2 source is disabled */
+
+#endif
--- /dev/null
+#ifndef __msp430_headers_tlv_h
+#define __msp430_headers_tlv_h
+
+/* tlv.h
+ *
+ * mspgcc project: MSP430 device headers
+ * tlv structures
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@users.sf.net>
+ *
+ * $Id: tlv.h,v 1.2 2009/01/11 23:11:48 sb-sf Exp $
+ */
+
+/* Switches: none */
+
+
+/* TLV Calibration Data Structure */
+#define TAG_DCO_30 0x01 /* Tag for DCO30 Calibration Data */
+#define TAG_ADC12_1 0x10 /* Tag for ADC12_1 Calibration Data */
+#define TAG_EMPTY 0xFE /* Tag for Empty Data Field in Calibration Data */
+
+#define TLV_CHECKSUM_ 0x10C0 /* TLV CHECK SUM */
+sfrw(TLV_CHECKSUM, TLV_CHECKSUM_);
+#define TLV_DCO_30_TAG_ 0x10F6 /* TLV TAG_DCO30 TAG */
+sfrb(TLV_DCO_30_TAG, TLV_DCO_30_TAG_);
+#define TLV_DCO_30_LEN_ 0x10F7 /* TLV TAG_DCO30 LEN */
+sfrb(TLV_DCO_30_LEN, TLV_DCO_30_LEN_);
+#define TLV_ADC12_1_TAG_ 0x10DA /* TLV ADC12_1 TAG */
+sfrb(TLV_ADC12_1_TAG, TLV_ADC12_1_TAG_);
+#define TLV_ADC12_1_LEN_ 0x10DB /* TLV ADC12_1 LEN */
+sfrb(TLV_ADC12_1_LEN, TLV_ADC12_1_LEN_);
+
+#define CAL_ADC_25T85 0x0007 /* Index for 2.5V/85Deg Cal. Value */
+#define CAL_ADC_25T30 0x0006 /* Index for 2.5V/30Deg Cal. Value */
+#define CAL_ADC_25VREF_FACTOR 0x0005 /* Index for 2.5V Ref. Factor */
+#define CAL_ADC_15T85 0x0004 /* Index for 1.5V/85Deg Cal. Value */
+#define CAL_ADC_15T30 0x0003 /* Index for 1.5V/30Deg Cal. Value */
+#define CAL_ADC_15VREF_FACTOR 0x0002 /* Index for ADC 1.5V Ref. Factor */
+#define CAL_ADC_OFFSET 0x0001 /* Index for ADC Offset */
+#define CAL_ADC_GAIN_FACTOR 0x0000 /* Index for ADC Gain Factor */
+
+#define CALDCO_16MHZ_ 0x10F8 /* DCOCTL Calibration Data for 16MHz */
+sfrb(CALDCO_16MHZ, CALDCO_16MHZ_);
+#define CALBC1_16MHZ_ 0x10F9 /* BCSCTL1 Calibration Data for 16MHz */
+sfrb(CALBC1_16MHZ, CALBC1_16MHZ_);
+#define CALDCO_12MHZ_ 0x10FA /* DCOCTL Calibration Data for 12MHz */
+sfrb(CALDCO_12MHZ, CALDCO_12MHZ_);
+#define CALBC1_12MHZ_ 0x10FB /* BCSCTL1 Calibration Data for 12MHz */
+sfrb(CALBC1_12MHZ, CALBC1_12MHZ_);
+#define CALDCO_8MHZ_ 0x10FC /* DCOCTL Calibration Data for 8MHz */
+sfrb(CALDCO_8MHZ, CALDCO_8MHZ_);
+#define CALBC1_8MHZ_ 0x10FD /* BCSCTL1 Calibration Data for 8MHz */
+sfrb(CALBC1_8MHZ, CALBC1_8MHZ_);
+#define CALDCO_1MHZ_ 0x10FE /* DCOCTL Calibration Data for 1MHz */
+sfrb(CALDCO_1MHZ, CALDCO_1MHZ_);
+#define CALBC1_1MHZ_ 0x10FF /* BCSCTL1 Calibration Data for 1MHz */
+sfrb(CALBC1_1MHZ, CALBC1_1MHZ_);
+
+#define CAL_DCO_16MHZ 0x0000 /* Index for DCOCTL Calibration Data for 16MHz */
+#define CAL_BC1_16MHZ 0x0001 /* Index for BCSCTL1 Calibration Data for 16MHz */
+#define CAL_DCO_12MHZ 0x0002 /* Index for DCOCTL Calibration Data for 12MHz */
+#define CAL_BC1_12MHZ 0x0003 /* Index for BCSCTL1 Calibration Data for 12MHz */
+#define CAL_DCO_8MHZ 0x0004 /* Index for DCOCTL Calibration Data for 8MHz */
+#define CAL_BC1_8MHZ 0x0005 /* Index for BCSCTL1 Calibration Data for 8MHz */
+#define CAL_DCO_1MHZ 0x0006 /* Index for DCOCTL Calibration Data for 1MHz */
+#define CAL_BC1_1MHZ 0x0007 /* Index for BCSCTL1 Calibration Data for 1MHz */
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+typedef enum
+{
+ DCO_30_TAG = 0x01,
+ ADC12_1_TAG = 0x10,
+ EMPTY_TAG = 0xFE,
+
+} tlv_tags_t;
+
+typedef struct
+{
+ unsigned char tag;
+ unsigned char length;
+ struct
+ {
+ unsigned char DCO_16MHZ;
+ unsigned char BC1_16MHZ;
+ unsigned char DCO_12MHZ;
+ unsigned char BC1_12MHZ;
+ unsigned char DCO_8MHZ;
+ unsigned char BC1_8MHZ;
+ unsigned char DCO_1MHZ;
+ unsigned char BC1_1MHZ;
+ } value;
+} const dco_30_tag_t;
+
+typedef struct
+{
+ unsigned char tag;
+ unsigned char length;
+ struct
+ {
+ unsigned int ADC_GAIN_FACTOR;
+ unsigned int ADC_OFFSET;
+ unsigned int ADC_15VREF_FACTOR;
+ unsigned int ADC_15T30;
+ unsigned int ADC_15T85;
+ unsigned int ADC_25VREF_FACTOR;
+ unsigned int ADC_25T30;
+ unsigned int ADC_25T85;
+ } value;
+} const adc12_1_tag_t;
+
+typedef struct
+{
+ unsigned char tag;
+ unsigned char length;
+} const empty_tag_t;
+
+struct
+{
+ unsigned int checksum;
+ empty_tag_t empty;
+ unsigned int dummy[11];
+ adc12_1_tag_t adc12_1;
+ dco_30_tag_t dco_30;
+} const volatile TLV_bits asm("0x10c0");
+#endif // __ASSEMBLER__
+
+#endif /* __msp430_headers_tlv_h */
--- /dev/null
+#ifndef __msp430_headers_unified_clock_system_h
+#define __msp430_headers_unified_clock_system_h
+
+/* unified_clock_system.h
+ *
+ * mspgcc project: MSP430 device headers
+ * UNIFIED_CLOCK_SYSTEM module header
+ *
+ * (c) 2002 by S. Balling <praktikum@innoventis.de>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: unified_clock_system.h,v 1.1 2009/06/04 21:55:18 cliechti Exp $
+ */
+
+/* Switches:
+__MSP430_HAS_UCS__
+*/
+
+#if defined(__MSP430_HAS_UCS__)
+#define UCSCTL0_ 0x0160
+sfrw (UCSCTL0,UCSCTL0_);
+#define UCSCTL0_L_ 0x0160
+sfrb (UCSCTL0_L,UCSCTL0_L_);
+#define UCSCTL0_H_ 0x0161
+sfrb (UCSCTL0_H,UCSCTL0_H_);
+#define UCSCTL1_ 0x0162
+sfrw (UCSCTL1,UCSCTL1_);
+#define UCSCTL1_L_ 0x0162
+sfrb (UCSCTL1_L,UCSCTL1_L_);
+#define UCSCTL1_H_ 0x0163
+sfrb (UCSCTL1_H,UCSCTL1_H_);
+#define UCSCTL2_ 0x0164
+sfrw (UCSCTL2,UCSCTL2_);
+#define UCSCTL2_L_ 0x0164
+sfrb (UCSCTL2_L,UCSCTL2_L_);
+#define UCSCTL2_H_ 0x0165
+sfrb (UCSCTL2_H,UCSCTL2_H_);
+#define UCSCTL3_ 0x0166
+sfrw (UCSCTL3,UCSCTL3_);
+#define UCSCTL3_L_ 0x0166
+sfrb (UCSCTL3_L,UCSCTL3_L_);
+#define UCSCTL3_H_ 0x0167
+sfrb (UCSCTL3_H,UCSCTL3_H_);
+#define UCSCTL4_ 0x0168
+sfrw (UCSCTL4,UCSCTL4_);
+#define UCSCTL4_L_ 0x0168
+sfrb (UCSCTL4_L,UCSCTL4_L_);
+#define UCSCTL4_H_ 0x0169
+sfrb (UCSCTL4_H,UCSCTL4_H_);
+#define UCSCTL5_ 0x016A
+sfrw (UCSCTL5,UCSCTL5_);
+#define UCSCTL5_L_ 0x016A
+sfrb (UCSCTL5_L,UCSCTL5_L_);
+#define UCSCTL5_H_ 0x016B
+sfrb (UCSCTL5_H,UCSCTL5_H_);
+#define UCSCTL6_ 0x016C
+sfrw (UCSCTL6,UCSCTL6_);
+#define UCSCTL6_L_ 0x016C
+sfrb (UCSCTL6_L,UCSCTL6_L_);
+#define UCSCTL6_H_ 0x016D
+sfrb (UCSCTL6_H,UCSCTL6_H_);
+#define UCSCTL7_ 0x016E
+sfrw (UCSCTL7,UCSCTL7_);
+#define UCSCTL7_L_ 0x016E
+sfrb (UCSCTL7_L,UCSCTL7_L_);
+#define UCSCTL7_H_ 0x016F
+sfrb (UCSCTL7_H,UCSCTL7_H_);
+#define UCSCTL8_ 0x0170
+sfrw (UCSCTL8,UCSCTL8_);
+#define UCSCTL8_L_ 0x0170
+sfrb (UCSCTL8_L,UCSCTL8_L_);
+#define UCSCTL8_H_ 0x0171
+sfrb (UCSCTL8_H,UCSCTL8_H_);
+
+/* UCSCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */
+#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */
+#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */
+#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */
+#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */
+#define DCO0 (0x0100) /* DCO TAP Bit : 0 */
+#define DCO1 (0x0200) /* DCO TAP Bit : 1 */
+#define DCO2 (0x0400) /* DCO TAP Bit : 2 */
+#define DCO3 (0x0800) /* DCO TAP Bit : 3 */
+#define DCO4 (0x1000) /* DCO TAP Bit : 4 */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */
+#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */
+#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */
+#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */
+#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */
+#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */
+#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */
+#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */
+#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL1 Control Bits */
+#define DISMOD (0x0001) /* Disable Modulation */
+#define DCOR (0x0002) /* DCO External Resistor Select */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */
+#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */
+#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL1 Control Bits */
+#define DISMOD_L (0x0001) /* Disable Modulation */
+#define DCOR_L (0x0002) /* DCO External Resistor Select */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */
+#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */
+#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL1 Control Bits */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */
+#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */
+#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */
+#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */
+#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */
+#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */
+#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */
+#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */
+
+/* UCSCTL2 Control Bits */
+#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */
+#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */
+#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */
+#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */
+#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */
+#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */
+#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */
+#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */
+#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */
+#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */
+#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */
+#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL2 Control Bits */
+#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */
+#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */
+#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */
+#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */
+#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */
+#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */
+#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */
+#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL2 Control Bits */
+#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */
+#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */
+#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */
+#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */
+#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */
+#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */
+#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */
+#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */
+#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */
+#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */
+#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */
+#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */
+#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */
+#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */
+#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */
+#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */
+#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */
+
+/* UCSCTL3 Control Bits */
+#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */
+#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */
+#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */
+#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */
+#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL3 Control Bits */
+#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */
+#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */
+#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */
+#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */
+#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL3 Control Bits */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0100) /* RESERVED */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */
+#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */
+#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */
+#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */
+#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */
+#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */
+#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */
+#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */
+#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */
+#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */
+#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */
+#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */
+#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */
+#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */
+#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */
+#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */
+#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */
+#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */
+#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */
+#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */
+#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */
+#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */
+#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */
+#define SELREF__VLOCLK (0x0010) /* Multiply Selected Loop Freq. By VLOCLK */
+#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */
+#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */
+
+/* UCSCTL4 Control Bits */
+#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
+#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
+#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
+#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
+#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
+#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
+#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL4 Control Bits */
+#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
+#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
+#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
+#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
+#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL4 Control Bits */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
+#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
+#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define SELM_0 (0x0000) /* MCLK Source Select 0 */
+#define SELM_1 (0x0001) /* MCLK Source Select 1 */
+#define SELM_2 (0x0002) /* MCLK Source Select 2 */
+#define SELM_3 (0x0003) /* MCLK Source Select 3 */
+#define SELM_4 (0x0004) /* MCLK Source Select 4 */
+#define SELM_5 (0x0005) /* MCLK Source Select 5 */
+#define SELM_6 (0x0006) /* MCLK Source Select 6 */
+#define SELM_7 (0x0007) /* MCLK Source Select 7 */
+#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
+#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
+#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */
+#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
+#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */
+#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */
+
+#define SELS_0 (0x0000) /* SMCLK Source Select 0 */
+#define SELS_1 (0x0010) /* SMCLK Source Select 1 */
+#define SELS_2 (0x0020) /* SMCLK Source Select 2 */
+#define SELS_3 (0x0030) /* SMCLK Source Select 3 */
+#define SELS_4 (0x0040) /* SMCLK Source Select 4 */
+#define SELS_5 (0x0050) /* SMCLK Source Select 5 */
+#define SELS_6 (0x0060) /* SMCLK Source Select 6 */
+#define SELS_7 (0x0070) /* SMCLK Source Select 7 */
+#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
+#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
+#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */
+#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
+#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */
+#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */
+
+#define SELA_0 (0x0000) /* ACLK Source Select 0 */
+#define SELA_1 (0x0100) /* ACLK Source Select 1 */
+#define SELA_2 (0x0200) /* ACLK Source Select 2 */
+#define SELA_3 (0x0300) /* ACLK Source Select 3 */
+#define SELA_4 (0x0400) /* ACLK Source Select 4 */
+#define SELA_5 (0x0500) /* ACLK Source Select 5 */
+#define SELA_6 (0x0600) /* ACLK Source Select 6 */
+#define SELA_7 (0x0700) /* ACLK Source Select 7 */
+#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
+#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
+#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */
+#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
+#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */
+#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */
+
+/* UCSCTL5 Control Bits */
+#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
+#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
+#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
+#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
+#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
+#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
+#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
+//#define RESERVED (0x0800) /* RESERVED */
+#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */
+#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */
+#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL5 Control Bits */
+#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
+#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
+#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
+#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
+#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL5 Control Bits */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
+#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
+#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
+//#define RESERVED (0x0800) /* RESERVED */
+#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */
+#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */
+#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
+#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
+#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
+#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
+#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
+#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
+#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */
+#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */
+#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
+#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
+#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
+#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
+#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
+#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
+
+#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
+#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
+#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
+#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
+#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
+#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
+#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */
+#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */
+#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
+#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
+#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
+#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
+#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
+#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
+
+#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
+#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
+#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
+#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
+#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
+#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
+#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */
+#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */
+#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
+#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
+#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
+#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
+#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
+#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
+
+#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */
+#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */
+#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */
+#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */
+#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */
+#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */
+#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */
+#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */
+#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */
+#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */
+#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */
+#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */
+#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */
+#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */
+
+/* UCSCTL6 Control Bits */
+#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
+#define SMCLKOFF (0x0002) /* SMCLK Off */
+#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */
+#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */
+#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
+#define XTS (0x0020) /* 1: Selects high-freq. oscillator */
+#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
+#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
+#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
+//#define RESERVED (0x2000) /* RESERVED */
+#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */
+#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */
+
+/* UCSCTL6 Control Bits */
+#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
+#define SMCLKOFF_L (0x0002) /* SMCLK Off */
+#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */
+#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */
+#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
+#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
+#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
+#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+
+/* UCSCTL6 Control Bits */
+#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
+//#define RESERVED (0x0200) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
+//#define RESERVED (0x2000) /* RESERVED */
+#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */
+#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */
+
+#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */
+#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */
+#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */
+#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */
+#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
+#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
+#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
+#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
+#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */
+#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */
+#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */
+#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */
+
+/* UCSCTL7 Control Bits */
+#define DCOFFG (0x0001) /* DCO Fault Flag */
+#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
+#define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
+#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */
+#define FLLULIFG (0x0010) /* FLL Unlock Interrupt Flag */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define FLLUNLOCK0 (0x0100) /* FLL Unlock Bit 0 */
+#define FLLUNLOCK1 (0x0200) /* FLL Unlock Bit 1 */
+#define FLLUNLOCKHIS0 (0x0400) /* FLL Unlock History Bit 0 */
+#define FLLUNLOCKHIS1 (0x08000) /* FLL Unlock History Bit 1 */
+#define FLLULIE (0x01000) /* FLL Unlock Interrupt Enable */
+#define FLLWARNEN (0x02000) /* FLL Warning Enable */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL7 Control Bits */
+#define DCOFFG_L (0x0001) /* DCO Fault Flag */
+#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
+#define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */
+#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */
+#define FLLULIFG_L (0x0010) /* FLL Unlock Interrupt Flag */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL7 Control Bits */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define FLLUNLOCK0_H (0x0001) /* FLL Unlock Bit 0 */
+#define FLLUNLOCK1_H (0x0002) /* FLL Unlock Bit 1 */
+#define FLLUNLOCKHIS0_H (0x0004) /* FLL Unlock History Bit 0 */
+#define FLLUNLOCKHIS1_H (0x0080) /* FLL Unlock History Bit 1 */
+#define FLLULIE_H (0x0010) /* FLL Unlock Interrupt Enable */
+#define FLLWARNEN_H (0x0020) /* FLL Warning Enable */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL8 Control Bits */
+#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
+#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
+#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
+#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */
+#define IFCLKSEN (0x0010) /* Enable Interface Clock slow down mechanism */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SMCLK_FSEN (0x0100) /* Enable fail safe enable for SMCLK source */
+#define ACLK_FSEN (0x0200) /* Enable fail safe enable for ACLK source */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL8 Control Bits */
+#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
+#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
+#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
+#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */
+#define IFCLKSEN_L (0x0010) /* Enable Interface Clock slow down mechanism */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* UCSCTL8 Control Bits */
+//#define RESERVED (0x0020) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SMCLK_FSEN_H (0x0001) /* Enable fail safe enable for SMCLK source */
+#define ACLK_FSEN_H (0x0002) /* Enable fail safe enable for ACLK source */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+#endif
+
+#endif /*__msp430_headers_unified_clock_system_h */
--- /dev/null
+#ifndef __msp430_headers_usart_h
+#define __msp430_headers_usart_h
+
+/* usart.h
+ *
+ * mspgcc project: MSP430 device headers
+ * USART module header
+ *
+ * (c) 2002 by M. P. Ashton <data@ieee.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: usart.h,v 1.12 2007/02/16 13:07:23 cliechti Exp $
+ */
+
+/* Switches:
+
+__MSP430_HAS_I2C__ - if device has USART0 with I2C feature
+__MSP430_HAS_UART1__ - if device has USART1
+
+*/
+
+/* -------- Common USART bit definitions */
+
+#define PENA 0x80 /* UCTL */
+#define PEV 0x40
+#define SPB 0x20 /* to distinguish from stackpointer SP */
+#define CHAR 0x10
+#define LISTEN 0x08 /* Loopback */
+#define SYNC 0x04 /* USART synchronous/asynchronous */
+#define MM 0x02
+#define SWRST 0x01
+
+#define CKPH 0x80 /* UTCTL */
+#define CKPL 0x40
+#define SSEL1 0x20
+#define SSEL0 0x10
+#define URXSE 0x08
+#define TXWAKE 0x04
+#define STC 0x02
+#define TXEPT 0x01
+
+#define FE 0x80 /* URCTL */
+#define PE 0x40
+#define OE 0x20
+#define BRK 0x10
+#define URXEIE 0x08
+#define URXWIE 0x04
+#define RXWAKE 0x02
+#define RXERR 0x01
+
+/* Aliases by mspgcc */
+#define SSEL_0 0x00 /* UCLKI */
+#define SSEL_1 0x10 /* ACLK */
+#define SSEL_2 0x20 /* SMCLK */
+#define SSEL_3 0x30 /* SMCLK */
+
+#define SSEL_UCLKI SSEL_0
+#define SSEL_ACLK SSEL_1
+#define SSEL_SMCLK SSEL_2
+/*#define SSEL_SMCLK SSEL_3*/
+
+#if defined(__MSP430_HAS_UART0__)
+/*UART0 ME/IE/IFG is different on F12x and F13x/F14x devices.
+ With these defines, the right sfrs are choosen automaticaly.
+ These defines should only be used with bit set and clear
+ instructions as the real ME/IE/IFG sfrs might be modified
+ somewhere else too!
+ e.g.:
+ ME1 = ME1_INIT; //enable all other modules first
+ ME2 = ME2_INIT; //enable all other modules first
+ U0ME |= UTXE0|URXE0; //and then the USART0
+*/
+#if defined(__msp430x12x) || defined(__msp430x12x2)
+ #define U0ME ME2 /* RX and TX module enable */
+ #define U0IE IE2 /* RX and TX interrupt of UART0 */
+ #define U0IFG IFG2 /* RX and TX interrupt flags of UART0 */
+#else /* not a __msp430x12x or __msp430x12x2 */
+ #define U0ME ME1 /* RX and TX module enable */
+ #define U0IE IE1 /* RX and TX interrupt of UART0 */
+ #define U0IFG IFG1 /* RX and TX interrupt flags of UART0 */
+#endif
+#endif /*__MSP430_HAS_UART0__*/
+
+/* UART1 aliases for consistency with UART0 */
+#if defined(__MSP430_HAS_UART1__)
+ #define U1ME ME2 /* RX and TX module enable */
+ #define U1IE IE2 /* RX and TX interrupt of UART1 */
+ #define U1IFG IFG2 /* RX and TX interrupt flags of UART1 */
+#endif
+
+
+#if defined(__MSP430_HAS_UART0__)
+
+/* -------- USART 0 */
+
+#define U0CTL_ 0x0070 /* UART 0 Control */
+sfrb(U0CTL, U0CTL_);
+#define U0TCTL_ 0x0071 /* UART 0 Transmit Control */
+sfrb(U0TCTL, U0TCTL_);
+#define U0RCTL_ 0x0072 /* UART 0 Receive Control */
+sfrb(U0RCTL, U0RCTL_);
+#define U0MCTL_ 0x0073 /* UART 0 Modulation Control */
+sfrb(U0MCTL, U0MCTL_);
+#define U0BR0_ 0x0074 /* UART 0 Baud Rate 0 */
+sfrb(U0BR0, U0BR0_);
+#define U0BR1_ 0x0075 /* UART 0 Baud Rate 1 */
+sfrb(U0BR1, U0BR1_);
+#define U0RXBUF_ 0x0076 /* UART 0 Receive Buffer */
+sfrb(U0RXBUF, U0RXBUF_);
+#define U0TXBUF_ 0x0077 /* UART 0 Transmit Buffer */
+sfrb(U0TXBUF, U0TXBUF_);
+
+/* Alternate register names */
+
+#define UCTL_ 0x0070 /* UART Control */
+sfrb(UCTL, UCTL_);
+#define UTCTL_ 0x0071 /* UART Transmit Control */
+sfrb(UTCTL, UTCTL_);
+#define URCTL_ 0x0072 /* UART Receive Control */
+sfrb(URCTL, URCTL_);
+#define UMCTL_ 0x0073 /* UART Modulation Control */
+sfrb(UMCTL, UMCTL_);
+#define UBR0_ 0x0074 /* UART Baud Rate 0 */
+sfrb(UBR0, UBR0_);
+#define UBR1_ 0x0075 /* UART Buad Rate 1 */
+sfrb(UBR1, UBR1_);
+#define RXBUF_ 0x0076 /* UART Receive Buffer */
+sfrb(RXBUF, RXBUF_);
+#define TXBUF_ 0x0077 /* UART Transmit Buffer */
+sfrb(TXBUF, TXBUF_);
+
+#define UCTL0_ 0x0070 /* UART 0 Control */
+sfrb(UCTL0, UCTL0_);
+#define UTCTL0_ 0x0071 /* UART 0 Transmit Control */
+sfrb(UTCTL0, UTCTL0_);
+#define URCTL0_ 0x0072 /* UART 0 Receive Control */
+sfrb(URCTL0, URCTL0_);
+#define UMCTL0_ 0x0073 /* UART 0 Modulation Control */
+sfrb(UMCTL0, UMCTL0_);
+#define UBR00_ 0x0074 /* UART 0 Baud Rate 0 */
+sfrb(UBR00, UBR00_);
+#define UBR10_ 0x0075 /* UART 0 Baud Rate 1 */
+sfrb(UBR10, UBR10_);
+#define RXBUF0_ 0x0076 /* UART 0 Receive Buffer */
+sfrb(RXBUF0, RXBUF0_);
+#define TXBUF0_ 0x0077 /* UART 0 Transmit Buffer */
+sfrb(TXBUF0, TXBUF0_);
+
+#define UCTL_0_ 0x0070 /* UART 0 Control */
+sfrb(UCTL_0, UCTL_0_);
+#define UTCTL_0_ 0x0071 /* UART 0 Transmit Control */
+sfrb(UTCTL_0, UTCTL_0_);
+#define URCTL_0_ 0x0072 /* UART 0 Receive Control */
+sfrb(URCTL_0, URCTL_0_);
+#define UMCTL_0_ 0x0073 /* UART 0 Modulation Control */
+sfrb(UMCTL_0, UMCTL_0_);
+#define UBR0_0_ 0x0074 /* UART 0 Baud Rate 0 */
+sfrb(UBR0_0, UBR0_0_);
+#define UBR1_0_ 0x0075 /* UART 0 Baud Rate 1 */
+sfrb(UBR1_0, UBR1_0_);
+#define RXBUF_0_ 0x0076 /* UART 0 Receive Buffer */
+sfrb(RXBUF_0, RXBUF_0_);
+#define TXBUF_0_ 0x0077 /* UART 0 Transmit Buffer */
+sfrb(TXBUF_0, TXBUF_0_);
+
+#if defined(__MSP430_HAS_I2C__)
+
+/* USART 0 Control */
+#define RXDMAEN 0x80 /* Receive DMA enable */
+#define TXDMAEN 0x40 /* Transmit DMA enable */
+#define I2C 0x20 /* USART I2C */
+#define XA 0x10 /* I2C extended addressing */
+/* LISTEN - as for non I2C version */
+/* SYNC - as for non I2C version */
+#define MST 0x02 /* I2C master */
+#define I2CEN 0x01 /* I2C enable */
+
+#define STTIE 0x80 /* Start condition */
+#define GCIE 0x40 /* General call */
+#define TXRDYIE 0x20 /* Transmit ready (transmit register empty) */
+#define RXRDYIE 0x10 /* Receive ready (data received) */
+#define ARDYIE 0x08 /* Access ready (operation complete) */
+#define OAIE 0x04 /* Own address */
+#define NACKIE 0x02 /* No acknowledge */
+#define ALIE 0x01 /* Arbitration lost */
+
+#define STTIFG 0x80 /* Start condition */
+#define GCIFG 0x40 /* General call */
+#define TXRDYIFG 0x20 /* Transmit ready (transmit register empty) */
+#define RXRDYIFG 0x10 /* Receive ready (data received) */
+#define ARDYIFG 0x08 /* Access ready (operation complete) */
+#define OAIFG 0x04 /* Own address */
+#define NACKIFG 0x02 /* No acknowledge */
+#define ALIFG 0x01 /* Arbitration lost */
+
+#define I2CWORD 0x80 /* Word data mode */
+#define I2CRM 0x40 /* Repeat mode */
+#define I2CSSEL1 0x20 /* Clock select bit 1 */
+#define I2CSSEL0 0x10 /* Clock select bit 0 */
+#define I2CTRX 0x08 /* Transmit */
+#define I2CSTB 0x04 /* Start byte mode */
+#define I2CSTP 0x02 /* Stop bit */
+#define I2CSTT 0x01 /* Start bit */
+
+#define I2CSSEL_0 (0<<4) /* I2C clock select 0: UCLK */
+#define I2CSSEL_1 (1<<4) /* I2C clock select 1: ACLK */
+#define I2CSSEL_2 (2<<4) /* I2C clock select 2: SMCLK */
+#define I2CSSEL_3 (3<<4) /* I2C clock select 3: SMCLK */
+
+#define I2CMM_0 0 /* Master mode 0 */
+#define I2CMM_1 (SST) /* Master mode 1 */
+#define I2CMM_2 (STP|SST) /* Master mode 2 */
+#define I2CMM_3 (RM|STT) /* Master mode 3 */
+#define I2CMM_4 (STP) /* Master mode 4 */
+
+#define I2CBUSY 0x20 /* I2C module not idle */
+#define I2CSCLLOW 0x10 /* SCL being held low */
+#define I2CSBD 0x08 /* Received byte */
+#define I2CTXUDF 0x04 /* Transmit underflow */
+#define I2CRXOVR 0x02 /* Receiver overrun */
+#define I2CBB 0x01 /* Bus busy */
+
+
+#define I2CIV_NONE 0x00 /* I2C interrupt vector: No interrupt pending */
+#define I2CIV_AL 0x02 /* I2C interrupt vector: Arbitration lost (ALIFG) */
+#define I2CIV_NACK 0x04 /* I2C interrupt vector: No acknowledge (NACKIFG) */
+#define I2CIV_OA 0x06 /* I2C interrupt vector: Own address (OAIFG) */
+#define I2CIV_ARDY 0x08 /* I2C interrupt vector: Access ready (ARDYIFG) */
+#define I2CIV_RXRDY 0x0A /* I2C interrupt vector: Receive ready (RXRDYIFG) */
+#define I2CIV_TXRDY 0x0C /* I2C interrupt vector: Transmit ready (TXRDYIFG) */
+#define I2CIV_GC 0x0E /* I2C interrupt vector: General call (GCIFG) */
+#define I2CIV_STT 0x10 /* I2C interrupt vector: Start condition (STTIFG) */
+
+#define I2CIE_ 0x0050 /* I2C interrupt enable */
+sfrb(I2CIE, I2CIE_);
+#define I2CIFG_ 0x0051 /* I2C interrupt flag */
+sfrb(I2CIFG, I2CIFG_);
+#define I2CNDAT_ 0x0052 /* I2C data count */
+sfrb(I2CNDAT, I2CNDAT_);
+#define I2CTCTL_ 0x0071 /* I2C transfer control */
+sfrb(I2CTCTL, I2CTCTL_);
+#define I2CDCTL_ 0x0072 /* I2C data control */
+sfrb(I2CDCTL, I2CDCTL_);
+#define I2CPSC_ 0x0073 /* I2C PSC */
+sfrb(I2CPSC, I2CPSC_);
+#define I2CSCLH_ 0x0074 /* I2C SCLH */
+sfrb(I2CSCLH, I2CSCLH_);
+#define I2CSCLL_ 0x0075 /* I2C SCLL */
+sfrb(I2CSCLL, I2CSCLL_);
+#define I2CDRB_ 0x0076 /* I2C data for byte access */
+sfrb(I2CDRB, I2CDRB_);
+#define I2CDRW_ 0x0076 /* I2C data for word access */
+sfrw(I2CDRW, I2CDRW_);
+#define I2COA_ 0x0118 /* I2C own address */
+sfrw(I2COA, I2COA_);
+#define I2CSA_ 0x011A /* I2C slave address */
+sfrw(I2CSA, I2CSA_);
+#define I2CIV_ 0x011C /* I2C interrupt vector */
+sfrw(I2CIV, I2CIV_);
+
+/* Backwards compatibility to older versions of the header file.
+ Please consider using the new name I2CDRB.
+ */
+#define I2CDR_ 0x0076 /* I2C data for byte access */
+sfrb(I2CDR, I2CDR_);
+
+/* Aliases by mspgcc */
+#define I2CSSEL_UCLK I2CSSEL_0 /* I2C clock select 0: UCLK */
+#define I2CSSEL_ACLK I2CSSEL_1 /* I2C clock select 1: ACLK */
+#define I2CSSEL_SMCLK I2CSSEL_2 /* I2C clock select 2: SMCLK */
+//~ #define I2CSSEL_SMCLK I2CSSEL_3 /* I2C clock select 3: SMCLK */
+
+#endif /* __MSP430_HAS_I2C__ */
+#endif /*__MSP430_HAS_UART0__*/
+
+#if defined(__MSP430_HAS_UART1__)
+
+/* -------- USART1 */
+
+#define U1CTL_ 0x0078 /* UART 1 Control */
+sfrb(U1CTL, U1CTL_);
+#define U1TCTL_ 0x0079 /* UART 1 Transmit Control */
+sfrb(U1TCTL, U1TCTL_);
+#define U1RCTL_ 0x007A /* UART 1 Receive Control */
+sfrb(U1RCTL, U1RCTL_);
+#define U1MCTL_ 0x007B /* UART 1 Modulation Control */
+sfrb(U1MCTL, U1MCTL_);
+#define U1BR0_ 0x007C /* UART 1 Baud Rate 0 */
+sfrb(U1BR0, U1BR0_);
+#define U1BR1_ 0x007D /* UART 1 Baud Rate 1 */
+sfrb(U1BR1, U1BR1_);
+#define U1RXBUF_ 0x007E /* UART 1 Receive Buffer */
+sfrb(U1RXBUF, U1RXBUF_);
+#define U1TXBUF_ 0x007F /* UART 1 Transmit Buffer */
+sfrb(U1TXBUF, U1TXBUF_);
+
+#define UCTL1_ 0x0078 /* UART 1 Control */
+sfrb(UCTL1, UCTL1_);
+#define UTCTL1_ 0x0079 /* UART 1 Transmit Control */
+sfrb(UTCTL1, UTCTL1_);
+#define URCTL1_ 0x007A /* UART 1 Receive Control */
+sfrb(URCTL1, URCTL1_);
+#define UMCTL1_ 0x007B /* UART 1 Modulation Control */
+sfrb(UMCTL1, UMCTL1_);
+#define UBR01_ 0x007C /* UART 1 Baud Rate 0 */
+sfrb(UBR01, UBR01_);
+#define UBR11_ 0x007D /* UART 1 Baud Rate 1 */
+sfrb(UBR11, UBR11_);
+#define RXBUF1_ 0x007E /* UART 1 Receive Buffer */
+sfrb(RXBUF1, RXBUF1_);
+#define TXBUF1_ 0x007F /* UART 1 Transmit Buffer */
+sfrb(TXBUF1, TXBUF1_);
+
+#define UCTL_1_ 0x0078 /* UART 1 Control */
+sfrb(UCTL_1, UCTL_1_);
+#define UTCTL_1_ 0x0079 /* UART 1 Transmit Control */
+sfrb(UTCTL_1, UTCTL_1_);
+#define URCTL_1_ 0x007A /* UART 1 Receive Control */
+sfrb(URCTL_1, URCTL_1_);
+#define UMCTL_1_ 0x007B /* UART 1 Modulation Control */
+sfrb(UMCTL_1, UMCTL_1_);
+#define UBR0_1_ 0x007C /* UART 1 Baud Rate 0 */
+sfrb(UBR0_1, UBR0_1_);
+#define UBR1_1_ 0x007D /* UART 1 Baud Rate 1 */
+sfrb(UBR1_1, UBR1_1_);
+#define RXBUF_1_ 0x007E /* UART 1 Receive Buffer */
+sfrb(RXBUF_1, RXBUF_1_);
+#define TXBUF_1_ 0x007F /* UART 1 Transmit Buffer */
+sfrb(TXBUF_1, TXBUF_1_);
+
+#endif /* __MSP430_HAS_UART1__ */
+
+#endif
--- /dev/null
+#if !defined(__msp430_headers_usci_h__)
+#define __msp430_headers_usci_h__
+
+/* usi.h
+ *
+ * mspgcc project: MSP430 device headers
+ * USCI module header
+ *
+ * (c) 2006 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: usci.h,v 1.7 2009/06/04 21:55:18 cliechti Exp $
+ *
+ * 2008-02-05 - modifications by G.Lemm <msp430@daqtix.com>
+ * - added UC1IE and UC1IFG registers
+ * - added UC*1*IE and UC*1*IFG bit definitions
+ * 2009-05-19 - modifications by S. Balling <praktikum@innoventis.de>
+ * - added switch for USCI0
+ * - added USCI0_5
+ * - added USCI1_5
+ * - added USCI2_5
+ * - added USCI3_5
+ */
+
+/* Switches:
+__MSP430_HAS_USCI0__ - if device has USCI0
+__MSP430_HAS_USCI1__ - if device has USCI1
+__MSP430_HAS_USCI0_5__ - if device has USCI0 and is part of family 5
+__MSP430_HAS_USCI1_5__ - if device has USCI1 and is part of family 5
+__MSP430_HAS_USCI2_5__ - if device has USCI2 and is part of family 5
+__MSP430_HAS_USCI3_5__ - if device has USCI3 and is part of family 5
+
+*/
+
+#define USIPE7 (0x80) /* USI Port Enable Px.7 */
+#define USIPE6 (0x40) /* USI Port Enable Px.6 */
+#define USIPE5 (0x20) /* USI Port Enable Px.5 */
+#define USILSB (0x10) /* USI LSB first 1:LSB / 0:MSB */
+#define USIMST (0x08) /* USI Master Select 0:Slave / 1:Master */
+#define USIGE (0x04) /* USI General Output Enable Latch */
+#define USIOE (0x02) /* USI Output Enable */
+#define USISWRST (0x01) /* USI Software Reset */
+
+#define USICKPH (0x80) /* USI Sync. Mode: Clock Phase */
+#define USII2C (0x40) /* USI I2C Mode */
+#define USISTTIE (0x20) /* USI START Condition interrupt enable */
+#define USIIE (0x10) /* USI Counter Interrupt enable */
+#define USIAL (0x08) /* USI Arbitration Lost */
+#define USISTP (0x04) /* USI STOP Condition received */
+#define USISTTIFG (0x02) /* USI START Condition interrupt Flag */
+#define USIIFG (0x01) /* USI Counter Interrupt Flag */
+
+#define USIDIV2 (0x80) /* USI Clock Divider 2 */
+#define USIDIV1 (0x40) /* USI Clock Divider 1 */
+#define USIDIV0 (0x20) /* USI Clock Divider 0 */
+#define USISSEL2 (0x10) /* USI Clock Source Select 2 */
+#define USISSEL1 (0x08) /* USI Clock Source Select 1 */
+#define USISSEL0 (0x04) /* USI Clock Source Select 0 */
+#define USICKPL (0x02) /* USI Clock Polarity 0:Inactive=Low / 1:Inactive=High */
+#define USISWCLK (0x01) /* USI Software Clock */
+
+#define USIDIV_0 (0x00) /* USI Clock Divider: 0 */
+#define USIDIV_1 (0x20) /* USI Clock Divider: 1 */
+#define USIDIV_2 (0x40) /* USI Clock Divider: 2 */
+#define USIDIV_3 (0x60) /* USI Clock Divider: 3 */
+#define USIDIV_4 (0x80) /* USI Clock Divider: 4 */
+#define USIDIV_5 (0xA0) /* USI Clock Divider: 5 */
+#define USIDIV_6 (0xC0) /* USI Clock Divider: 6 */
+#define USIDIV_7 (0xE0) /* USI Clock Divider: 7 */
+
+#define USISSEL_0 (0x00) /* USI Clock Source: 0 */
+#define USISSEL_1 (0x04) /* USI Clock Source: 1 */
+#define USISSEL_2 (0x08) /* USI Clock Source: 2 */
+#define USISSEL_3 (0x0C) /* USI Clock Source: 3 */
+#define USISSEL_4 (0x10) /* USI Clock Source: 4 */
+#define USISSEL_5 (0x14) /* USI Clock Source: 5 */
+#define USISSEL_6 (0x18) /* USI Clock Source: 6 */
+#define USISSEL_7 (0x1C) /* USI Clock Source: 7 */
+
+#define USISCLREL (0x80) /* USI SCL Released */
+#define USI16B (0x40) /* USI 16 Bit Shift Register Enable */
+#define USIFGDC (0x20) /* USI Interrupt Flag don't clear */
+#define USICNT4 (0x10) /* USI Bit Count 4 */
+#define USICNT3 (0x08) /* USI Bit Count 3 */
+#define USICNT2 (0x04) /* USI Bit Count 2 */
+#define USICNT1 (0x02) /* USI Bit Count 1 */
+#define USICNT0 (0x01) /* USI Bit Count 0 */
+
+// UART-Mode Bits
+#define UCPEN (0x80) /* Async. Mode: Parity enable */
+#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
+#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
+#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
+#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
+#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
+#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
+#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
+
+// SPI-Mode Bits
+#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
+#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
+#define UCMST (0x08) /* Sync. Mode: Master Select */
+
+// I2C-Mode Bits
+#define UCA10 (0x80) /* 10-bit Address Mode */
+#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
+#define UCMM (0x20) /* Multi-Master Environment */
+//#define res (0x10) /* reserved */
+#define UCMODE_0 (0<<1) /* Sync. Mode: USCI Mode: 0 */
+#define UCMODE_1 (1<<1) /* Sync. Mode: USCI Mode: 1 */
+#define UCMODE_2 (2<<1) /* Sync. Mode: USCI Mode: 2 */
+#define UCMODE_3 (3<<1) /* Sync. Mode: USCI Mode: 3 */
+
+// UART-Mode Bits
+#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE (0x20) /* RX Error interrupt enable */
+#define UCBRKIE (0x10) /* Break interrupt enable */
+#define UCDORM (0x08) /* Dormant (Sleep) Mode */
+#define UCTXADDR (0x04) /* Send next Data as Address */
+#define UCTXBRK (0x02) /* Send next Data as Break */
+#define UCSWRST (0x01) /* USCI Software Reset */
+
+// SPI-Mode Bits
+//#define res (0x20) /* reserved */
+//#define res (0x10) /* reserved */
+//#define res (0x08) /* reserved */
+//#define res (0x04) /* reserved */
+//#define res (0x02) /* reserved */
+
+// I2C-Mode Bits
+//#define res (0x20) /* reserved */
+#define UCTR (0x10) /* Transmit/Receive Select/Flag */
+#define UCTXNACK (0x08) /* Transmit NACK */
+#define UCTXSTP (0x04) /* Transmit STOP */
+#define UCTXSTT (0x02) /* Transmit START */
+#define UCSSEL_0 (0<<6) /* USCI 0 Clock Source: 0 */
+#define UCSSEL_1 (1<<6) /* USCI 0 Clock Source: 1 */
+#define UCSSEL_2 (2<<6) /* USCI 0 Clock Source: 2 */
+#define UCSSEL_3 (3<<6) /* USCI 0 Clock Source: 3 */
+
+#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
+#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
+#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
+#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
+#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
+#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
+
+#define UCBRF_0 (0x0<<4) /* USCI First Stage Modulation: 0 */
+#define UCBRF_1 (0x1<<4) /* USCI First Stage Modulation: 1 */
+#define UCBRF_2 (0x2<<4) /* USCI First Stage Modulation: 2 */
+#define UCBRF_3 (0x3<<4) /* USCI First Stage Modulation: 3 */
+#define UCBRF_4 (0x4<<4) /* USCI First Stage Modulation: 4 */
+#define UCBRF_5 (0x5<<4) /* USCI First Stage Modulation: 5 */
+#define UCBRF_6 (0x6<<4) /* USCI First Stage Modulation: 6 */
+#define UCBRF_7 (0x7<<4) /* USCI First Stage Modulation: 7 */
+#define UCBRF_8 (0x8<<4) /* USCI First Stage Modulation: 8 */
+#define UCBRF_9 (0x9<<4) /* USCI First Stage Modulation: 9 */
+#define UCBRF_10 (0xA<<4) /* USCI First Stage Modulation: A */
+#define UCBRF_11 (0xB<<4) /* USCI First Stage Modulation: B */
+#define UCBRF_12 (0xC<<4) /* USCI First Stage Modulation: C */
+#define UCBRF_13 (0xD<<4) /* USCI First Stage Modulation: D */
+#define UCBRF_14 (0xE<<4) /* USCI First Stage Modulation: E */
+#define UCBRF_15 (0xF<<4) /* USCI First Stage Modulation: F */
+
+#define UCBRS_0 (0<<1) /* USCI Second Stage Modulation: 0 */
+#define UCBRS_1 (1<<1) /* USCI Second Stage Modulation: 1 */
+#define UCBRS_2 (2<<1) /* USCI Second Stage Modulation: 2 */
+#define UCBRS_3 (3<<1) /* USCI Second Stage Modulation: 3 */
+#define UCBRS_4 (4<<1) /* USCI Second Stage Modulation: 4 */
+#define UCBRS_5 (5<<1) /* USCI Second Stage Modulation: 5 */
+#define UCBRS_6 (6<<1) /* USCI Second Stage Modulation: 6 */
+#define UCBRS_7 (7<<1) /* USCI Second Stage Modulation: 7 */
+
+#define UCLISTEN (0x80) /* USCI Listen mode */
+#define UCFE (0x40) /* USCI Frame Error Flag */
+#define UCOE (0x20) /* USCI Overrun Error Flag */
+#define UCPE (0x10) /* USCI Parity Error Flag */
+#define UCBRK (0x08) /* USCI Break received */
+#define UCRXERR (0x04) /* USCI RX Error Flag */
+#define UCADDR (0x02) /* USCI Address received Flag */
+#define UCBUSY (0x01) /* USCI Busy Flag */
+#define UCIDLE (0x02) /* USCI Idle line detected Flag */
+
+//#define res (0x80) /* reserved */
+//#define res (0x40) /* reserved */
+//#define res (0x20) /* reserved */
+//#define res (0x10) /* reserved */
+#define UCNACKIE (0x08) /* NACK Condition interrupt enable */
+#define UCSTPIE (0x04) /* STOP Condition interrupt enable */
+#define UCSTTIE (0x02) /* START Condition interrupt enable */
+#define UCALIE (0x01) /* Arbitration Lost interrupt enable */
+
+#define UCSCLLOW (0x40) /* SCL low */
+#define UCGC (0x20) /* General Call address received Flag */
+#define UCBBUSY (0x10) /* Bus Busy Flag */
+#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */
+#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */
+#define UCSTTIFG (0x02) /* START Condition interrupt Flag */
+#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */
+
+#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
+#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
+
+#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
+#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
+
+//#define res (0x80) /* reserved */
+//#define res (0x40) /* reserved */
+#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
+#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
+#define UCSTOE (0x08) /* Sync-Field Timeout error */
+#define UCBTOE (0x04) /* Break Timeout error */
+//#define res (0x02) /* reserved */
+#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
+
+#define UCGCEN (0x8000) /* I2C General Call enable */
+#define UCOA9 (0x0200) /* I2C Own Address 9 */
+#define UCOA8 (0x0100) /* I2C Own Address 8 */
+#define UCOA7 (0x0080) /* I2C Own Address 7 */
+#define UCOA6 (0x0040) /* I2C Own Address 6 */
+#define UCOA5 (0x0020) /* I2C Own Address 5 */
+#define UCOA4 (0x0010) /* I2C Own Address 4 */
+#define UCOA3 (0x0008) /* I2C Own Address 3 */
+#define UCOA2 (0x0004) /* I2C Own Address 2 */
+#define UCOA1 (0x0002) /* I2C Own Address 1 */
+#define UCOA0 (0x0001) /* I2C Own Address 0 */
+
+#define UCSA9 (0x0200) /* I2C Slave Address 9 */
+#define UCSA8 (0x0100) /* I2C Slave Address 8 */
+#define UCSA7 (0x0080) /* I2C Slave Address 7 */
+#define UCSA6 (0x0040) /* I2C Slave Address 6 */
+#define UCSA5 (0x0020) /* I2C Slave Address 5 */
+#define UCSA4 (0x0010) /* I2C Slave Address 4 */
+#define UCSA3 (0x0008) /* I2C Slave Address 3 */
+#define UCSA2 (0x0004) /* I2C Slave Address 2 */
+#define UCSA1 (0x0002) /* I2C Slave Address 1 */
+#define UCSA0 (0x0001) /* I2C Slave Address 0 */
+
+/* Aliases by mspgcc */
+#define UCSSEL_UCLKI UCSSEL_0
+#define UCSSEL_ACLK UCSSEL_1
+#define UCSSEL_SMCLK UCSSEL_2
+
+#if defined(__MSP430_HAS_USCI0__)
+
+/* -------- USCI0 */
+
+#define UCA0CTL0_ 0x0060 /* USCI A0 Control Register 0 */
+sfrb(UCA0CTL0, UCA0CTL0_);
+#define UCA0CTL1_ 0x0061 /* USCI A0 Control Register 1 */
+sfrb(UCA0CTL1, UCA0CTL1_);
+#define UCA0BR0_ 0x0062 /* USCI A0 Baud Rate 0 */
+sfrb(UCA0BR0, UCA0BR0_);
+#define UCA0BR1_ 0x0063 /* USCI A0 Baud Rate 1 */
+sfrb(UCA0BR1, UCA0BR1_);
+#define UCA0MCTL_ 0x0064 /* USCI A0 Modulation Control */
+sfrb(UCA0MCTL, UCA0MCTL_);
+#define UCA0STAT_ 0x0065 /* USCI A0 Status Register */
+sfrb(UCA0STAT, UCA0STAT_);
+#define UCA0RXBUF_ 0x0066 /* USCI A0 Receive Buffer */
+/*READ_ONLY*/ sfrb(UCA0RXBUF, UCA0RXBUF_);
+#define UCA0TXBUF_ 0x0067 /* USCI A0 Transmit Buffer */
+sfrb(UCA0TXBUF, UCA0TXBUF_);
+#define UCA0ABCTL_ 0x005D /* USCI A0 Auto baud/LIN Control */
+sfrb(UCA0ABCTL, UCA0ABCTL_);
+#define UCA0IRTCTL_ 0x005E /* USCI A0 IrDA Transmit Control */
+sfrb(UCA0IRTCTL, UCA0IRTCTL_);
+#define UCA0IRRCTL_ 0x005F /* USCI A0 IrDA Receive Control */
+sfrb(UCA0IRRCTL, UCA0IRRCTL_);
+
+#define UCB0CTL0_ 0x0068 /* USCI B0 Control Register 0 */
+sfrb(UCB0CTL0, UCB0CTL0_);
+#define UCB0CTL1_ 0x0069 /* USCI B0 Control Register 1 */
+sfrb(UCB0CTL1, UCB0CTL1_);
+#define UCB0BR0_ 0x006A /* USCI B0 Baud Rate 0 */
+sfrb(UCB0BR0, UCB0BR0_);
+#define UCB0BR1_ 0x006B /* USCI B0 Baud Rate 1 */
+sfrb(UCB0BR1, UCB0BR1_);
+#define UCB0I2CIE_ 0x006C /* USCI B0 I2C Interrupt Enable Register */
+sfrb(UCB0I2CIE, UCB0I2CIE_);
+#define UCB0STAT_ 0x006D /* USCI B0 Status Register */
+sfrb(UCB0STAT, UCB0STAT_);
+#define UCB0RXBUF_ 0x006E /* USCI B0 Receive Buffer */
+/*READ_ONLY*/ sfrb(UCB0RXBUF, UCB0RXBUF_);
+#define UCB0TXBUF_ 0x006F /* USCI B0 Transmit Buffer */
+sfrb(UCB0TXBUF, UCB0TXBUF_);
+#define UCB0I2COA_ 0x0118 /* USCI B0 I2C Own Address */
+sfrw(UCB0I2COA, UCB0I2COA_);
+#define UCB0I2CSA_ 0x011A /* USCI B0 I2C Slave Address */
+sfrw(UCB0I2CSA, UCB0I2CSA_);
+#endif /* __MSP430_HAS_USCI0__ */
+
+#if defined(__MSP430_HAS_USCI1__)
+
+/* -------- USCI1 */
+
+#define UCA1CTL0_ 0x00D0 /* USCI A1 Control Register 0 */
+sfrb(UCA1CTL0, UCA1CTL0_);
+#define UCA1CTL1_ 0x00D1 /* USCI A1 Control Register 1 */
+sfrb(UCA1CTL1, UCA1CTL1_);
+#define UCA1BR0_ 0x00D2 /* USCI A1 Baud Rate 0 */
+sfrb(UCA1BR0, UCA1BR0_);
+#define UCA1BR1_ 0x00D3 /* USCI A1 Baud Rate 1 */
+sfrb(UCA1BR1, UCA1BR1_);
+#define UCA1MCTL_ 0x00D4 /* USCI A1 Modulation Control */
+sfrb(UCA1MCTL, UCA1MCTL_);
+#define UCA1STAT_ 0x00D5 /* USCI A1 Status Register */
+sfrb(UCA1STAT, UCA1STAT_);
+#define UCA1RXBUF_ 0x00D6 /* USCI A1 Receive Buffer */
+/*READ_ONLY*/ sfrb(UCA1RXBUF, UCA1RXBUF_);
+#define UCA1TXBUF_ 0x00D7 /* USCI A1 Transmit Buffer */
+sfrb(UCA1TXBUF, UCA1TXBUF_);
+#define UCA1ABCTL_ 0x00CD /* USCI A1 Auto baud/LIN Control */
+sfrb(UCA1ABCTL, UCA1ABCTL_);
+#define UCA1IRTCTL_ 0x00CE /* USCI A1 IrDA Transmit Control */
+sfrb(UCA1IRTCTL, UCA1IRTCTL_);
+#define UCA1IRRCTL_ 0x00CF /* USCI A1 IrDA Receive Control */
+sfrb(UCA1IRRCTL, UCA1IRRCTL_);
+
+#define UCB1CTL0_ 0x00D8 /* USCI B1 Control Register 0 */
+sfrb(UCB1CTL0, UCB1CTL0_);
+#define UCB1CTL1_ 0x00D9 /* USCI B1 Control Register 1 */
+sfrb(UCB1CTL1, UCB1CTL1_);
+#define UCB1BR0_ 0x00DA /* USCI B1 Baud Rate 0 */
+sfrb(UCB1BR0, UCB1BR0_);
+#define UCB1BR1_ 0x00DB /* USCI B1 Baud Rate 1 */
+sfrb(UCB1BR1, UCB1BR1_);
+#define UCB1I2CIE_ 0x00DC /* USCI B1 I2C Interrupt Enable Register */
+sfrb(UCB1I2CIE, UCB1I2CIE_);
+#define UCB1STAT_ 0x00DD /* USCI B1 Status Register */
+sfrb(UCB1STAT, UCB1STAT_);
+#define UCB1RXBUF_ 0x00DE /* USCI B1 Receive Buffer */
+/*READ_ONLY*/ sfrb(UCB1RXBUF, UCB1RXBUF_);
+#define UCB1TXBUF_ 0x00DF /* USCI B1 Transmit Buffer */
+sfrb(UCB1TXBUF, UCB1TXBUF_);
+#define UCB1I2COA_ 0x017C /* USCI B1 I2C Own Address */
+sfrw(UCB1I2COA, UCB1I2COA_);
+#define UCB1I2CSA_ 0x017E /* USCI B1 I2C Slave Address */
+sfrw(UCB1I2CSA, UCB1I2CSA_);
+
+#define UC1IE_ 0x0006 /* USCI A1/B1 Interrupt enable register */
+sfrb(UC1IE, UC1IE_);
+#define UC1IFG_ 0x0007 /* USCI A1/B1 Interrupt flag register */
+sfrb(UC1IFG, UC1IFG_);
+
+#define UCA1RXIE (1<<0)
+#define UCA1TXIE (1<<1)
+#define UCB1RXIE (1<<2)
+#define UCB1TXIE (1<<3)
+
+#define UCA1RXIFG (1<<0)
+#define UCA1TXIFG (1<<1)
+#define UCB1RXIFG (1<<2)
+#define UCB1TXIFG (1<<3)
+#endif /* __MSP430_HAS_USCI1__ */
+
+#if defined(__MSP430_HAS_USCI0_5__)
+
+/* -------- USCI0_5 */
+
+#define UCA0CTL0_ 0x05C1
+sfrb(UCA0CTL0, UCA0CTL0_);
+#define UCA0CTL1_ 0x05C0
+sfrb(UCA0CTL1, UCA0CTL1_);
+#define UCA0BR0_ 0x05C6
+sfrb(UCA0BR0, UCA0BR0_);
+#define UCA0BR1_ 0x05C7
+sfrb(UCA0BR1, UCA0BR1_);
+#define UCA0MCTL_ 0x05C8
+sfrb(UCA0MCTL, UCA0MCTL_);
+#define UCA0STAT_ 0x05CA
+sfrb(UCA0STAT, UCA0STAT_);
+#define UCA0RXBUF_ 0x05CC
+sfrb(UCA0RXBUF, UCA0RXBUF_);
+#define UCA0TXBUF_ 0x05CE
+sfrb(UCA0TXBUF, UCA0TXBUF_);
+#define UCA0ABCTL_ 0x05D0
+sfrb(UCA0ABCTL, UCA0ABCTL_);
+#define UCA0IRTCTL_ 0x05D2
+sfrb(UCA0IRTCTL, UCA0IRTCTL_);
+#define UCA0IRRCTL_ 0x05D3
+sfrb(UCA0IRRCTL, UCA0IRRCTL_);
+#define UCA0IE_ 0x05DC
+sfrb(UCA0IE, UCA0IE_);
+#define UCA0IFG_ 0x05DD
+sfrb(UCA0IFG, UCA0IFG_);
+#define UCA0IV_ 0x05DE
+sfrw(UCA0IV, UCA0IV_);
+#define UCA0IV_L_ 0x05DE
+sfrb(UCA0IV_L, UCA0IV_L_);
+#define UCA0IV_H_ 0x05DF
+sfrb(UCA0IV_H, UCA0IV_H_);
+
+#define UCB0CTL0_ 0x05E1
+sfrb(UCB0CTL0, UCB0CTL0_);
+#define UCB0CTL1_ 0x05E0
+sfrb(UCB0CTL1, UCB0CTL1_);
+#define UCB0BR0_ 0x05E6
+sfrb(UCB0BR0, UCB0BR0_);
+#define UCB0BR1_ 0x05E7
+sfrb(UCB0BR1, UCB0BR1_);
+#define UCB0MCTL_ 0x05E8
+sfrb(UCB0MCTL, UCB0MCTL_);
+#define UCB0STAT_ 0x05EA
+sfrb(UCB0STAT, UCB0STAT_);
+#define UCB0RXBUF_ 0x05EC
+sfrb(UCB0RXBUF, UCB0RXBUF_);
+#define UCB0TXBUF_ 0x05EE
+sfrb(UCB0TXBUF, UCB0TXBUF_);
+#define UCB0I2COA_ 0x05F0
+sfrb(UCB0I2COA, UCB0I2COA_);
+#define UCB0I2CSA_ 0x05F2
+sfrb(UCB0I2CSA, UCB0I2CSA_);
+#define UCB0IE_ 0x05FC
+sfrb(UCB0IE, UCB0IE_);
+#define UCB0IFG_ 0x05FD
+sfrb(UCB0IFG, UCB0IFG_);
+#define UCB0IV_ 0x05FE
+sfrw(UCB0IV, UCB0IV_);
+#define UCB0IV_L_ 0x05FE
+sfrb(UCB0IV_L, UCB0IV_L_);
+#define UCB0IV_H_ 0x05FF
+sfrb(UCB0IV_H, UCB0IV_H_);
+
+#endif /* __MSP430_HAS_USCI0_5__ */
+
+#if defined(__MSP430_HAS_USCI1_5__)
+
+/* -------- USCI1_5 */
+
+// tbd
+/*#define UCA1CTL0_ 0x0601
+#define UCA1CTL0_L 0x0601
+#define UCA1CTL0_H 0x0602
+#define UCA1CTL1_ 0x0600
+#define UCA1CTL1_L 0x0600
+#define UCA1CTL1_H 0x0601
+#define UCA1BR0_ 0x0606
+#define UCA1BR0_L 0x0606
+#define UCA1BR0_H 0x0607
+#define UCA1BR1_ 0x0607
+#define UCA1BR1_L 0x0607
+#define UCA1BR1_H 0x0608
+#define UCA1MCTL_ 0x0608
+#define UCA1MCTL_L 0x0608
+#define UCA1MCTL_H 0x0609
+#define UCA1STAT_ 0x060A
+#define UCA1STAT_L 0x060A
+#define UCA1STAT_H 0x060B
+#define UCA1RXBUF 0x060C
+#define UCA1RXBUF_L 0x060C
+#define UCA1RXBUF_H 0x060D
+#define UCA1TXBUF 0x060E
+#define UCA1TXBUF_L 0x060E
+#define UCA1TXBUF_H 0x060F
+#define UCA1ABCTL 0x0610
+#define UCA1ABCTL_L 0x0610
+#define UCA1ABCTL_H 0x0611
+#define UCA1IRTCTL 0x0612
+#define UCA1IRTCTL_L 0x0612
+#define UCA1IRTCTL_H 0x0613
+#define UCA1IRRCTL 0x0613
+#define UCA1IRRCTL_L 0x0613
+#define UCA1IRRCTL_H 0x0614
+#define UCA1IE_ 0x061C
+#define UCA1IE_L_ 0x061C
+#define UCA1IE_H_ 0x061D
+#define UCA1IFG_ 0x061D
+#define UCA1IFG_L 0x061D
+#define UCA1IFG_H 0x061E
+#define UCA1IV_ 0x061E
+#define UCA1IV_L_ 0x061E
+#define UCA1IV_H_ 0x061F
+#define UCB1CTL0_ 0x0621
+#define UCB1CTL0_L 0x0621
+#define UCB1CTL0_H 0x0622
+#define UCB1CTL1_ 0x0620
+#define UCB1CTL1_L 0x0620
+#define UCB1CTL1_H 0x0621
+#define UCB1BR0_ 0x0626
+#define UCB1BR0_L 0x0626
+#define UCB1BR0_H 0x0627
+#define UCB1BR1_ 0x0627
+#define UCB1BR1_L 0x0627
+#define UCB1BR1_H 0x0628
+#define UCB1STAT_ 0x062A
+#define UCB1STAT_L 0x062A
+#define UCB1STAT_H 0x062B
+#define UCB1RXBUF 0x062C
+#define UCB1RXBUF_L 0x062C
+#define UCB1RXBUF_H 0x062D
+#define UCB1TXBUF 0x062E
+#define UCB1TXBUF_L 0x062E
+#define UCB1TXBUF_H 0x062F
+#define UCB1I2COA 0x0630
+#define UCB1I2COA_L 0x0630
+#define UCB1I2COA_H 0x0631
+#define UCB1I2CSA 0x0632
+#define UCB1I2CSA_L 0x0632
+#define UCB1I2CSA_H 0x0633
+#define UCB1IE_ 0x063C
+#define UCB1IE_L_ 0x063C
+#define UCB1IE_H_ 0x063D
+#define UCB1IFG_ 0x063D
+#define UCB1IFG_L 0x063D
+#define UCB1IFG_H 0x063E
+#define UCB1IV_ 0x063E
+#define UCB1IV_L_ 0x063E
+#define UCB1IV_H_ 0x063F
+*/
+#endif /* __MSP430_HAS_USCI1_5__ */
+
+#if defined(__MSP430_HAS_USCI2_5__)
+
+/* -------- USCI2_5 */
+
+// tbd
+/*#define UCA2CTL0_ 0x0641
+#define UCA2CTL0_L 0x0641
+#define UCA2CTL0_H 0x0642
+#define UCA2CTL1_ 0x0640
+#define UCA2CTL1_L 0x0640
+#define UCA2CTL1_H 0x0641
+#define UCA2BR0_ 0x0646
+#define UCA2BR0_L 0x0646
+#define UCA2BR0_H 0x0647
+#define UCA2BR1_ 0x0647
+#define UCA2BR1_L 0x0647
+#define UCA2BR1_H 0x0648
+#define UCA2MCTL_ 0x0648
+#define UCA2MCTL_L 0x0648
+#define UCA2MCTL_H 0x0649
+#define UCA2STAT_ 0x064A
+#define UCA2STAT_L 0x064A
+#define UCA2STAT_H 0x064B
+#define UCA2RXBUF 0x064C
+#define UCA2RXBUF_L 0x064C
+#define UCA2RXBUF_H 0x064D
+#define UCA2TXBUF 0x064E
+#define UCA2TXBUF_L 0x064E
+#define UCA2TXBUF_H 0x064F
+#define UCA2ABCTL 0x0650
+#define UCA2ABCTL_L 0x0650
+#define UCA2ABCTL_H 0x0651
+#define UCA2IRTCTL 0x0652
+#define UCA2IRTCTL_L 0x0652
+#define UCA2IRTCTL_H 0x0653
+#define UCA2IRRCTL 0x0653
+#define UCA2IRRCTL_L 0x0653
+#define UCA2IRRCTL_H 0x0654
+#define UCA2IE_ 0x065C
+#define UCA2IE_L_ 0x065C
+#define UCA2IE_H_ 0x065D
+#define UCA2IFG_ 0x065D
+#define UCA2IFG_L 0x065D
+#define UCA2IFG_H 0x065E
+#define UCA2IV_ 0x065E
+#define UCA2IV_L_ 0x065E
+#define UCA2IV_H_ 0x065F
+#define UCB2CTL0_ 0x0661
+#define UCB2CTL0_L 0x0661
+#define UCB2CTL0_H 0x0662
+#define UCB2CTL1_ 0x0660
+#define UCB2CTL1_L 0x0660
+#define UCB2CTL1_H 0x0661
+#define UCB2BR0_ 0x0666
+#define UCB2BR0_L 0x0666
+#define UCB2BR0_H 0x0667
+#define UCB2BR1_ 0x0667
+#define UCB2BR1_L 0x0667
+#define UCB2BR1_H 0x0668
+#define UCB2STAT_ 0x066A
+#define UCB2STAT_L 0x066A
+#define UCB2STAT_H 0x066B
+#define UCB2RXBUF 0x066C
+#define UCB2RXBUF_L 0x066C
+#define UCB2RXBUF_H 0x066D
+#define UCB2TXBUF 0x066E
+#define UCB2TXBUF_L 0x066E
+#define UCB2TXBUF_H 0x066F
+#define UCB2I2COA 0x0670
+#define UCB2I2COA_L 0x0670
+#define UCB2I2COA_H 0x0671
+#define UCB2I2CSA 0x0672
+#define UCB2I2CSA_L 0x0672
+#define UCB2I2CSA_H 0x0673
+#define UCB2IE_ 0x067C
+#define UCB2IE_L_ 0x067C
+#define UCB2IE_H_ 0x067D
+#define UCB2IFG_ 0x067D
+#define UCB2IFG_L 0x067D
+#define UCB2IFG_H 0x067E
+#define UCB2IV_ 0x067E
+#define UCB2IV_L_ 0x067E
+#define UCB2IV_H_ 0x067F
+*/
+#endif /* __MSP430_HAS_USCI2_5__ */
+
+#if defined(__MSP430_HAS_USCI3_5__)
+
+/* -------- USCI3_5 */
+// tbd
+/*#define UCA3CTL0_ 0x0681
+#define UCA3CTL0_L 0x0681
+#define UCA3CTL0_H 0x0682
+#define UCA3CTL1_ 0x0680
+#define UCA3CTL1_L 0x0680
+#define UCA3CTL1_H 0x0681
+#define UCA3BR0_ 0x0686
+#define UCA3BR0_L 0x0686
+#define UCA3BR0_H 0x0687
+#define UCA3BR1_ 0x0687
+#define UCA3BR1_L 0x0687
+#define UCA3BR1_H 0x0688
+#define UCA3MCTL_ 0x0688
+#define UCA3MCTL_L 0x0688
+#define UCA3MCTL_H 0x0689
+#define UCA3STAT_ 0x068A
+#define UCA3STAT_L 0x068A
+#define UCA3STAT_H 0x068B
+#define UCA3RXBUF 0x068C
+#define UCA3RXBUF_L 0x068C
+#define UCA3RXBUF_H 0x068D
+#define UCA3TXBUF 0x068E
+#define UCA3TXBUF_L 0x068E
+#define UCA3TXBUF_H 0x068F
+#define UCA3ABCTL 0x0690
+#define UCA3ABCTL_L 0x0690
+#define UCA3ABCTL_H 0x0691
+#define UCA3IRTCTL 0x0692
+#define UCA3IRTCTL_L 0x0692
+#define UCA3IRTCTL_H 0x0693
+#define UCA3IRRCTL 0x0693
+#define UCA3IRRCTL_L 0x0693
+#define UCA3IRRCTL_H 0x0694
+#define UCA3IE_ 0x069C
+#define UCA3IE_L_ 0x069C
+#define UCA3IE_H_ 0x069D
+#define UCA3IFG_ 0x069D
+#define UCA3IFG_L 0x069D
+#define UCA3IFG_H 0x069E
+#define UCA3IV_ 0x069E
+#define UCA3IV_L_ 0x069E
+#define UCA3IV_H_ 0x069F
+#define UCB3CTL0_ 0x06A1
+#define UCB3CTL0_L 0x06A1
+#define UCB3CTL0_H 0x06A2
+#define UCB3CTL1_ 0x06A0
+#define UCB3CTL1_L 0x06A0
+#define UCB3CTL1_H 0x06A1
+#define UCB3BR0_ 0x06A6
+#define UCB3BR0_L 0x06A6
+#define UCB3BR0_H 0x06A7
+#define UCB3BR1_ 0x06A7
+#define UCB3BR1_L 0x06A7
+#define UCB3BR1_H 0x06A8
+#define UCB3STAT_ 0x06AA
+#define UCB3STAT_L 0x06AA
+#define UCB3STAT_H 0x06AB
+#define UCB3RXBUF 0x06AC
+#define UCB3RXBUF_L 0x06AC
+#define UCB3RXBUF_H 0x06AD
+#define UCB3TXBUF 0x06AE
+#define UCB3TXBUF_L 0x06AE
+#define UCB3TXBUF_H 0x06AF
+#define UCB3I2COA 0x06B0
+#define UCB3I2COA_L 0x06B0
+#define UCB3I2COA_H 0x06B1
+#define UCB3I2CSA 0x06B2
+#define UCB3I2CSA_L 0x06B2
+#define UCB3I2CSA_H 0x06B3
+#define UCB3IE_ 0x06BC
+#define UCB3IE_L_ 0x06BC
+#define UCB3IE_H_ 0x06BD
+#define UCB3IFG_ 0x06BD
+#define UCB3IFG_L 0x06BD
+#define UCB3IFG_H 0x06BE
+#define UCB3IV_ 0x06BE
+#define UCB3IV_L_ 0x06BE
+#define UCB3IV_H_ 0x06BF
+*/
+#endif /* __MSP430_HAS_USCI3_5__ */
+
+#endif
--- /dev/null
+#if !defined(__msp430_headers_usi_h__)
+#define __msp430_headers_usi_h__
+
+/* usi.h
+ *
+ * mspgcc project: MSP430 device headers
+ * USI module header
+ *
+ * (c) 2005 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * $Id: usi.h,v 1.4 2007/08/20 13:02:33 coppice Exp $
+ */
+
+/* Switches:
+
+*/
+
+#define USICTL0_ 0x0078 /* USI Control Register 0 */
+sfrb(USICTL0, USICTL0_);
+#define USICTL1_ 0x0079 /* USI Control Register 1 */
+sfrb(USICTL1, USICTL1_);
+#define USICKCTL_ 0x007A /* USI Clock Control Register */
+sfrb(USICKCTL, USICKCTL_);
+#define USICNT_ 0x007B /* USI Bit Counter Register */
+sfrb(USICNT, USICNT_);
+#define USISRL_ 0x007C /* USI Low Byte Shift Register */
+sfrb(USISRL, USISRL_);
+#define USISRH_ 0x007D /* USI High Byte Shift Register */
+sfrb(USISRH, USISRH_);
+#define USICTL_ 0x0078 /* USI Control Register */
+sfrw(USICTL, USICTL_);
+
+#define USICCTL_ 0x007A /* USI Clock and Counter Control Register */
+sfrw(USICCTL, USICCTL_);
+
+#define USISR_ 0x007C /* USI Shift Register */
+sfrw(USISR, USISR_);
+
+#define USIPE7 (0x80) /* USI Port Enable Px.7 */
+#define USIPE6 (0x40) /* USI Port Enable Px.6 */
+#define USIPE5 (0x20) /* USI Port Enable Px.5 */
+#define USILSB (0x10) /* USI LSB first 1:LSB / 0:MSB */
+#define USIMST (0x08) /* USI Master Select 0:Slave / 1:Master */
+#define USIGE (0x04) /* USI General Output Enable Latch */
+#define USIOE (0x02) /* USI Output Enable */
+#define USISWRST (0x01) /* USI Software Reset */
+
+#define USICKPH (0x80) /* USI Sync. Mode: Clock Phase */
+#define USII2C (0x40) /* USI I2C Mode */
+#define USISTTIE (0x20) /* USI START Condition interrupt enable */
+#define USIIE (0x10) /* USI Counter Interrupt enable */
+#define USIAL (0x08) /* USI Arbitration Lost */
+#define USISTP (0x04) /* USI STOP Condition received */
+#define USISTTIFG (0x02) /* USI START Condition interrupt Flag */
+#define USIIFG (0x01) /* USI Counter Interrupt Flag */
+
+#define USIDIV2 (0x80) /* USI Clock Divider 2 */
+#define USIDIV1 (0x40) /* USI Clock Divider 1 */
+#define USIDIV0 (0x20) /* USI Clock Divider 0 */
+#define USISSEL2 (0x10) /* USI Clock Source Select 2 */
+#define USISSEL1 (0x08) /* USI Clock Source Select 1 */
+#define USISSEL0 (0x04) /* USI Clock Source Select 0 */
+#define USICKPL (0x02) /* USI Clock Polarity 0:Inactive=Low / 1:Inactive=High */
+#define USISWCLK (0x01) /* USI Software Clock */
+
+#define USIDIV_0 (0x00) /* USI Clock Divider: 0 Divide by 1 */
+#define USIDIV_1 (0x20) /* USI Clock Divider: 1 Divide by 2 */
+#define USIDIV_2 (0x40) /* USI Clock Divider: 2 Divide by 4 */
+#define USIDIV_3 (0x60) /* USI Clock Divider: 3 Divide by 8 */
+#define USIDIV_4 (0x80) /* USI Clock Divider: 4 Divide by 16 */
+#define USIDIV_5 (0xA0) /* USI Clock Divider: 5 Divide by 32 */
+#define USIDIV_6 (0xC0) /* USI Clock Divider: 6 Divide by 64 */
+#define USIDIV_7 (0xE0) /* USI Clock Divider: 7 Divide by 128 */
+
+#define USISSEL_0 (0x00) /* USI Clock Source: 0 SCLK */
+#define USISSEL_1 (0x04) /* USI Clock Source: 1 ACLK */
+#define USISSEL_2 (0x08) /* USI Clock Source: 2 SMCLK */
+#define USISSEL_3 (0x0C) /* USI Clock Source: 3 SMCLK */
+#define USISSEL_4 (0x10) /* USI Clock Source: 4 USISWCLK bit*/
+#define USISSEL_5 (0x14) /* USI Clock Source: 5 TACCR0 */
+#define USISSEL_6 (0x18) /* USI Clock Source: 6 TACCR1 */
+#define USISSEL_7 (0x1C) /* USI Clock Source: 7 TACCR2 */
+
+#define USISCLREL (0x80) /* USI SCL Released */
+#define USI16B (0x40) /* USI 16 Bit Shift Register Enable */
+#define USIIFGCC (0x20) /* USI Interrupt Flag Clear Control */
+#define USICNT4 (0x10) /* USI Bit Count 4 */
+#define USICNT3 (0x08) /* USI Bit Count 3 */
+#define USICNT2 (0x04) /* USI Bit Count 2 */
+#define USICNT1 (0x02) /* USI Bit Count 1 */
+#define USICNT0 (0x01) /* USI Bit Count 0 */
+
+/* Aliases by mspgcc */
+#define USIDIV_DIV1 USIDIV_0 /* USI Clock Divider: 0 Divide by 1 */
+#define USIDIV_DIV2 USIDIV_1 /* USI Clock Divider: 1 Divide by 2 */
+#define USIDIV_DIV4 USIDIV_2 /* USI Clock Divider: 2 Divide by 4 */
+#define USIDIV_DIV8 USIDIV_3 /* USI Clock Divider: 3 Divide by 8 */
+#define USIDIV_DIV16 USIDIV_4 /* USI Clock Divider: 4 Divide by 16 */
+#define USIDIV_DIV32 USIDIV_5 /* USI Clock Divider: 5 Divide by 32 */
+#define USIDIV_DIV64 USIDIV_6 /* USI Clock Divider: 6 Divide by 64 */
+#define USIDIV_DIV128 USIDIV_7 /* USI Clock Divider: 7 Divide by 128 */
+
+#define USISSEL_SCLK USISSEL_0 /* USI Clock Source: 0 SCLK */
+#define USISSEL_ACLK USISSEL_1 /* USI Clock Source: 1 ACLK */
+#define USISSEL_SMCLK USISSEL_2 /* USI Clock Source: 2 SMCLK */
+//~ #define USISSEL_3 USISSEL_3 /* USI Clock Source: 3 SMCLK */
+#define USISSEL_USISWCLK USISSEL_4 /* USI Clock Source: 4 USISWCLK bit*/
+#define USISSEL_TACCR0 USISSEL_5 /* USI Clock Source: 5 TACCR0 */
+#define USISSEL_TACCR1 USISSEL_6 /* USI Clock Source: 6 TACCR1 */
+#define USISSEL_TACCR2 USISSEL_7 /* USI Clock Source: 7 TACCR2 */
+
+#endif
--- /dev/null
+#ifndef __MSP430_HEADERS_WDT_A_H
+#define __MSP430_HEADERS_WDT_A_H
+
+/* wdt_a.h
+ *
+ * mspgcc project: MSP430 device headers
+ * watchdog timer module
+ *
+ * (c) 2008 by Sergey A. Borshch <sb-sf@users.sf.net>
+ * Originally based in MSP430F543x datasheet (slas609)
+ * and MSP430x5xx Family User's Guide (slau208).
+ *
+ * $Id: wdt_a.h,v 1.6 2009/02/28 12:14:53 sb-sf Exp $
+ */
+
+/* Switches:
+
+__MSP430_WDT_A_BASE__ - base address of WDT_A module
+
+*/
+
+#define WDTCTL_ __MSP430_WDT_A_BASE__ + 0x0C /* Watchdog timer control register */
+sfrw(WDTCTL, WDTCTL_);
+
+/* WDTCTL */
+#define WDTPW (0x5A<<8) /* Watchdog timer password. Always read as 069h. Must be written as 05Ah, or a PUC will be generated */
+#define WDTHOLD (1<<7) /* Watchdog timer hold */
+#define WDTSSEL1 (1<<6) /* Watchdog timer clock source select */
+#define WDTSSEL0 (1<<5) /* Watchdog timer clock source select */
+#define WDTTMSEL (1<<4) /* Watchdog timer mode select */
+#define WDTCNTCL (1<<3) /* Watchdog timer counter clear */
+#define WDTIS2 (1<<2) /* Watchdog timer interval select */
+#define WDTIS1 (1<<1) /* Watchdog timer interval select */
+#define WDTIS0 (1<<0) /* Watchdog timer interval select */
+
+/* Aliases by mspgcc */
+#define WDTIS_0 (0<<0) /* Watchdog timer /2G */
+#define WDTIS_1 (1<<0) /* Watchdog timer /128M */
+#define WDTIS_2 (2<<0) /* Watchdog timer /8192K */
+#define WDTIS_3 (3<<0) /* Watchdog timer /512K */
+#define WDTIS_4 (4<<0) /* Watchdog timer /32K */
+#define WDTIS_5 (5<<0) /* Watchdog timer /8192 */
+#define WDTIS_6 (6<<0) /* Watchdog timer /512 */
+#define WDTIS_7 (7<<0) /* Watchdog timer /64 */
+
+#define WDTSSEL_0 (0<<5) /* Watchdog clock SMCLK */
+#define WDTSSEL_1 (1<<5) /* Watchdog clock ACLK */
+#define WDTSSEL_2 (2<<5) /* Watchdog clock VLOCLK */
+#define WDTSSEL_3 (3<<5) /* Watchdog clock X_CLK */
+
+/* WDT-interval times [1ms] coded with Bits 0-2 */
+/* WDT is clocked by fMCLK (assumed 1MHz) */
+#define WDT_SMDLY_2147S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_0) /* 2147s */
+#define WDT_SMDLY_134S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_1) /* 134s */
+#define WDT_SMDLY_8S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_2) /* 8.38s */
+#define WDT_SMDLY_500MS (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_3) /* 524ms */
+#define WDT_SMDLY_32 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_4) /* 32ms interval (default) */
+#define WDT_SMDLY_8 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_5) /* 8ms */
+#define WDT_SMDLY_0_5 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_6) /* 0.5ms */
+#define WDT_SMDLY_0_064 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_7) /* 0.064ms */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ADLY_65536S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_0) /* 65536s */
+#define WDT_ADLY_4096S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_1) /* 4096s */
+#define WDT_ADLY_256S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_2) /* 256s */
+#define WDT_ADLY_16S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_3) /* 16s */
+#define WDT_ADLY_1000 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_4) /* 1000ms */
+#define WDT_ADLY_250 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_5) /* 250ms */
+#define WDT_ADLY_16 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_6) /* 16ms */
+#define WDT_ADLY_1_9 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_7) /* 1.9ms */
+/* Watchdog mode -> reset after expired time */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_SMRST_2147S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_0) /* 2147s */
+#define WDT_SMRST_134S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_1) /* 134s */
+#define WDT_SMRST_8S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_2) /* 8.38s */
+#define WDT_SMRST_500MS (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_3) /* 524ms */
+#define WDT_SMRST_32 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_4) /* 32ms interval (default) */
+#define WDT_SMRST_8 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_5) /* 8ms */
+#define WDT_SMRST_0_5 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_6) /* 0.5ms */
+#define WDT_SMRST_0_064 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_7) /* 0.064ms */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ARST_65536S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_0) /* 65536s */
+#define WDT_ARST_4096S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_1) /* 4096s */
+#define WDT_ARST_256S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_2) /* 256s */
+#define WDT_ARST_16S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_3) /* 16s */
+#define WDT_ARST_1000 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_4) /* 1s */
+#define WDT_ARST_250 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_5) /* 250ms */
+#define WDT_ARST_16 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_6) /* 16ms */
+#define WDT_ARST_1_9 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_7) /* 1.9ms */
+
+#ifndef __ASSEMBLER__
+/* Structured declaration */
+
+#undef __xstr
+#undef __str
+#define __xstr(x) __str(x)
+#define __str(x) #x
+struct
+{
+ volatile unsigned
+ IS0:3,
+ CNTCL:1,
+ TMSEL:1,
+ SSEL:2,
+ HOLD:1,
+ PW:8
+} const WDTCTL_bits asm(__xstr(__MSP430_WDT_A_BASE__ + 0x0C)); /* Watchdog timer control register */
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __MSP430_HEADERS_SYS_H */
--- /dev/null
+#if !defined(__msp430x261x)
+#define __msp430x261x
+
+/* msp430x261x.h
+ *
+ * mspgcc project: MSP430 device headers
+ * MSP430x14x family header
+ *
+ * (c) 2007 by Steve Underwood <steveu@coppice.org>
+ * Originally based in part on work by Texas Instruments Inc.
+ *
+ * 2008-06-04 - TonyB (tony.borries@gmail.com)
+ * - Defined __MSP430_HAS_PORT7_R__ and __MSP430_HAS_PORT8_R__
+ *
+ * 2008-03-05 - modifications by MB <mbarnes@inf.ed.ac.uk>, based on msp430x24x.h (G.Lemm) and original msp430x24x (Steve Underwood).
+ * - defined __DisableCalData to get rid of assembler errors
+ * - added usci.h include
+ * - added __MSP430_HAS_USCI1__ define_
+ * - commented out usart.h (didn't take a close look if we still need it)
+ *
+ * 2008-05-22 cliechti
+ * - fix bugs with calibration data
+ * - took out __DisableCalData
+ */
+
+#include <iomacros.h>
+
+//~ #define __DisableCalData
+
+#define __MSP430_HAS_WDT__
+#define __MSP430_HAS_MPY__
+#define __MSP430_HAS_PORT1_R__
+#define __MSP430_HAS_PORT2_R__
+#define __MSP430_HAS_PORT3_R__
+#define __MSP430_HAS_PORT4_R__
+#define __MSP430_HAS_PORT5_R__
+#define __MSP430_HAS_PORT6_R__
+#define __MSP430_HAS_PORT7_R__
+#define __MSP430_HAS_PORT8_R__
+#define __MSP430_HAS_SVS__
+#define __MSP430_HAS_USCI__
+#define __MSP430_HAS_USCI0__
+#define __MSP430_HAS_USCI1__
+#define __MSP430_HAS_USCI_AB0__
+#define __MSP430_HAS_USCI_AB1__
+#define __MSP430_HAS_TA3__
+#define __MSP430_HAS_TB7__
+#define __MSP430_HAS_BC2__
+#define __MSP430_HAS_FLASH2__
+#define __MSP430_HAS_CAPLUS__
+#define __MSP430_HAS_ADC12__
+#define __MSP430_HAS_DMAX_3__
+#define __MSP430_HAS_DMAIV__
+#define __MSP430_HAS_DAC12__
+
+#include <msp430/mpy.h>
+#include <msp430/gpio.h>
+#include <msp430/svs.h>
+#include <msp430/usci.h>
+#include <msp430/timera.h>
+#include <msp430/timerb.h>
+#include <msp430/basic_clock.h>
+#include <msp430/flash.h>
+#include <msp430/compa.h>
+#include <msp430/adc12.h>
+#include <msp430/dac12.h>
+#include <msp430/dma.h>
+#include <msp430/common.h>
+
+#define IE1_ 0x0000 /* Interrupt Enable 1 */
+sfrb(IE1,IE1_);
+#define WDTIE (1<<0)
+#define OFIE (1<<1)
+#define NMIIE (1<<4)
+#define ACCVIE (1<<5)
+
+#define IFG1_ 0x0002 /* Interrupt Flag 1 */
+sfrb(IFG1,IFG1_);
+#define WDTIFG (1<<0)
+#define OFIFG (1<<1)
+#define PORIFG (1<<2)
+#define RSTIFG (1<<3)
+#define NMIIFG (1<<4)
+
+#define IE2_ 0x0001 /* Interrupt Enable 2 */
+sfrb(IE2,IE2_);
+#define UC0IE IE2
+#define UCA0RXIE (1<<0)
+#define UCA0TXIE (1<<1)
+#define UCB0RXIE (1<<2)
+#define UCB0TXIE (1<<3)
+
+#define IFG2_ 0x0003 /* Interrupt Flag 2 */
+sfrb(IFG2,IFG2_);
+#define UC0IFG IFG2
+#define UCA0RXIFG (1<<0)
+#define UCA0TXIFG (1<<1)
+#define UCB0RXIFG (1<<2)
+#define UCB0TXIFG (1<<3)
+
+/************************************************************
+* Calibration Data in Info Mem
+************************************************************/
+
+/* TLV Calibration Data Structure */
+#define TAG_DCO_30 0x01 /* Tag for DCO30 Calibration Data */
+#define TAG_ADC12_1 0x10 /* Tag for ADC12_1 Calibration Data */
+#define TAG_EMPTY 0xFE /* Tag for Empty Data Field in Calibration Data */
+
+#ifndef __DisableCalData
+#define TLV_CHECKSUM_ 0x10C0 /* TLV CHECK SUM */
+sfrw(TLV_CHECKSUM, TLV_CHECKSUM_);
+#define TLV_DCO_30_TAG_ 0x10F6 /* TLV TAG_DCO30 TAG */
+sfrb(TLV_DCO_30_TAG, TLV_DCO_30_TAG_);
+#define TLV_DCO_30_LEN_ 0x10F7 /* TLV TAG_DCO30 LEN */
+sfrb(TLV_DCO_30_LEN, TLV_DCO_30_LEN_);
+#define TLV_ADC12_1_TAG_ 0x10DA /* TLV ADC12_1 TAG */
+sfrb(TLV_ADC12_1_TAG, TLV_ADC12_1_TAG_);
+#define TLV_ADC12_1_LEN_ 0x10DB /* TLV ADC12_1 LEN */
+sfrb(TLV_ADC12_1_LEN, TLV_ADC12_1_LEN_);
+#endif
+
+#define CAL_ADC_25T85 0x0007 /* Index for 2.5V/85Deg Cal. Value */
+#define CAL_ADC_25T30 0x0006 /* Index for 2.5V/30Deg Cal. Value */
+#define CAL_ADC_25VREF_FACTOR 0x0005 /* Index for 2.5V Ref. Factor */
+#define CAL_ADC_15T85 0x0004 /* Index for 1.5V/85Deg Cal. Value */
+#define CAL_ADC_15T30 0x0003 /* Index for 1.5V/30Deg Cal. Value */
+#define CAL_ADC_15VREF_FACTOR 0x0002 /* Index for ADC 1.5V Ref. Factor */
+#define CAL_ADC_OFFSET 0x0001 /* Index for ADC Offset */
+#define CAL_ADC_GAIN_FACTOR 0x0000 /* Index for ADC Gain Factor */
+
+#define CAL_DCO_16MHZ 0x0000 /* Index for DCOCTL Calibration Data for 16MHz */
+#define CAL_BC1_16MHZ 0x0001 /* Index for BCSCTL1 Calibration Data for 16MHz */
+#define CAL_DCO_12MHZ 0x0002 /* Index for DCOCTL Calibration Data for 12MHz */
+#define CAL_BC1_12MHZ 0x0003 /* Index for BCSCTL1 Calibration Data for 12MHz */
+#define CAL_DCO_8MHZ 0x0004 /* Index for DCOCTL Calibration Data for 8MHz */
+#define CAL_BC1_8MHZ 0x0005 /* Index for BCSCTL1 Calibration Data for 8MHz */
+#define CAL_DCO_1MHZ 0x0006 /* Index for DCOCTL Calibration Data for 1MHz */
+#define CAL_BC1_1MHZ 0x0007 /* Index for BCSCTL1 Calibration Data for 1MHz */
+
+
+/************************************************************
+* Calibration Data in Info Mem
+************************************************************/
+
+#ifndef __DisableCalData
+
+#define CALDCO_16MHZ_ 0x10F8 /* DCOCTL Calibration Data for 16MHz */
+sfrb(CALDCO_16MHZ, CALDCO_16MHZ_);
+#define CALBC1_16MHZ_ 0x10F9 /* BCSCTL1 Calibration Data for 16MHz */
+sfrb(CALBC1_16MHZ, CALBC1_16MHZ_);
+#define CALDCO_12MHZ_ 0x10FA /* DCOCTL Calibration Data for 12MHz */
+sfrb(CALDCO_12MHZ, CALDCO_12MHZ_);
+#define CALBC1_12MHZ_ 0x10FB /* BCSCTL1 Calibration Data for 12MHz */
+sfrb(CALBC1_12MHZ, CALBC1_12MHZ_);
+#define CALDCO_8MHZ_ 0x10FC /* DCOCTL Calibration Data for 8MHz */
+sfrb(CALDCO_8MHZ, CALDCO_8MHZ_);
+#define CALBC1_8MHZ_ 0x10FD /* BCSCTL1 Calibration Data for 8MHz */
+sfrb(CALBC1_8MHZ, CALBC1_8MHZ_);
+#define CALDCO_1MHZ_ 0x10FE /* DCOCTL Calibration Data for 1MHz */
+sfrb(CALDCO_1MHZ, CALDCO_1MHZ_);
+#define CALBC1_1MHZ_ 0x10FF /* BCSCTL1 Calibration Data for 1MHz */
+sfrb(CALBC1_1MHZ, CALBC1_1MHZ_);
+
+#endif /* #ifndef __DisableCalData */
+
+#define RESERVED0_VECTOR 0 /* 0xFFC0 Reserved Int. Vector 0 */
+#define RESERVED1_VECTOR 2 /* 0xFFC2 Reserved Int. Vector 1 */
+#define RESERVED2_VECTOR 4 /* 0xFFC4 Reserved Int. Vector 2 */
+#define RESERVED3_VECTOR 6 /* 0xFFC6 Reserved Int. Vector 3 */
+#define RESERVED4_VECTOR 8 /* 0xFFC8 Reserved Int. Vector 4 */
+#define RESERVED5_VECTOR 10 /* 0xFFCA Reserved Int. Vector 5 */
+#define RESERVED6_VECTOR 12 /* 0xFFCC Reserved Int. Vector 6 */
+#define RESERVED7_VECTOR 14 /* 0xFFCE Reserved Int. Vector 7 */
+#define RESERVED8_VECTOR 16 /* 0xFFD0 Reserved Int. Vector 8 */
+#define RESERVED9_VECTOR 18 /* 0xFFD2 Reserved Int. Vector 9 */
+#define RESERVED10_VECTOR 20 /* 0xFFD4 Reserved Int. Vector 10 */
+#define RESERVED11_VECTOR 22 /* 0xFFD6 Reserved Int. Vector 11 */
+#define RESERVED12_VECTOR 24 /* 0xFFD8 Reserved Int. Vector 12 */
+#define RESERVED13_VECTOR 26 /* 0xFFDA Reserved Int. Vector 13 */
+#define DAC12_VECTOR 28 /* 0xFFDC DAC12 Vector */
+#define DMA_VECTOR 30 /* 0xFFDE DMA Vector */
+#define USCIAB1TX_VECTOR 32 /* 0xFFE0 USCI A1/B1 Transmit */
+#define USCIAB1RX_VECTOR 34 /* 0xFFE2 USCI A1/B1 Receive */
+#define PORT1_VECTOR 36 /* 0xFFE4 Port 1 */
+#define PORT2_VECTOR 38 /* 0xFFE6 Port 2 */
+#define RESERVED20_VECTOR 40 /* 0xFFE8 Reserved Int. Vector 20 */
+#define ADC12_VECTOR 42 /* 0xFFEA ADC */
+#define USCIAB0TX_VECTOR 44 /* 0xFFEC USCI A0/B0 Transmit */
+#define USCIAB0RX_VECTOR 46 /* 0xFFEE USCI A0/B0 Receive */
+#define TIMERA1_VECTOR 48 /* 0xFFF0 Timer A CC1-2, TA */
+#define TIMERA0_VECTOR 50 /* 0xFFF2 Timer A CC0 */
+#define WDT_VECTOR 52 /* 0xFFF4 Watchdog Timer */
+#define COMPARATORA_VECTOR 54 /* 0xFFF6 Comparator A */
+#define TIMERB1_VECTOR 56 /* 0xFFF8 Timer B CC1-6, TB */
+#define TIMERB0_VECTOR 58 /* 0xFFFA Timer B CC0 */
+#define NMI_VECTOR 60 /* 0xFFFC Non-maskable */
+
+
+#define ADC_VECTOR ADC12_VECTOR
+
+#define BSLSKEY_ 0xFFbE /* The address is used as bootstrap loader security key */
+#define BSLSKEY_DISABLE 0xAA55 /* Disables the BSL completely */
+#define BSLSKEY_NO_ERASE 0x0000 /* Disables the erasure of the flash if an invalid password is supplied */
+
+#endif /* #ifndef __msp430x261x */
projects / 430.git / commitdiff