Move default setting to usbio

diff --git a/python-lib/mpsse-test.py b/python-lib/mpsse-test.py
index ba0294191095ed9a2b4dd3cc7d0e03620bf0b42e..dae6e0a54e13b9ac782912be4e5255938f97e528 100755 (executable)
--- a/python-lib/mpsse-test.py
+++ b/python-lib/mpsse-test.py
@@ -42,7 +42,7 @@ def str2hex(x):
 #
 # devboard conversion constants
 #
-VREF = 2.5
+VREF = 2.5 #output of DAC Vref generator
 SETTLE_TIME = 250e-6
 
 # Supply current sense circuitry
@@ -140,9 +140,10 @@ def get_i_supply():
 ##############################################################################
 # Setup FTDI serial ports
 #
-spi0 = usbio.AtoiSPI0(1000e3) #port A
-
-spi1 = usbio.AtoiSPI1(1000e3)  #port B
+#spi0 = usbio.AtoiSPI0(1000e3) #port A
+#spi1 = usbio.AtoiSPI1(1000e3)  #port B
+spi0 = usbio.NullSPI(1000e3) #port A
+spi1 = usbio.NullSPI(1000e3)  #port B
 #spi1.context.pidle = spi1.context.pstop = 0xf8
 #spi1.Stop()
 
@@ -219,17 +220,17 @@ psdefaults()
 # default mode is dac.INPUT_UPDATE_SINGLE
 #
 dac = usbio.DAC_atoi(spi0, 'dac')
-dac.swreset()
+#dac.swreset()
 
 # reference is tied to ADC, do not power down
-dac.reference(dac.REF_FLEXIBLE_ALWAYS_ON)
+#dac.reference(dac.REF_FLEXIBLE_ALWAYS_ON)
 
 # CLR is tied high, explicitly ignore anyway
 #dac.CCR(dac.IGNORE_CLR)
 
 # power up all channels
-bitfield = 0xff
-dac.power(dac.POWER_ON, bitfield)
+#bitfield = 0xff
+#dac.power(dac.POWER_ON, bitfield)
 
 # set initial output voltages
 # before tuning
@@ -245,8 +246,8 @@ dac.vbias_buf(000e-3)
 
 # zero others
 # part A already POR's to 0 but...
-for i in range(5, 8):
-    dac.setv(i, 0.0)
+#for i in range(5, 8):
+#    dac.setv(i, 0.0)
 
 
 ##############################################################################