--- /dev/null
+# Makefile for stm32f4 Codec 2 test programs
+
+###################################################
+
+PROJ_NAME=stm32f4_codec2
+FLOAT_TYPE=hard
+
+###################################################
+
+BINPATH=~/sat/bin
+CC=$(BINPATH)/arm-none-eabi-gcc
+OBJCOPY=$(BINPATH)/arm-none-eabi-objcopy
+SIZE=$(BINPATH)/arm-none-eabi-size
+
+###################################################
+
+CFLAGS = -std=gnu99 -g -O2 -Wall -Tstm32_flash.ld -DSTM32F4XX -DCORTEX_M4
+CFLAGS += -mlittle-endian -mthumb -mthumb-interwork -nostartfiles -mcpu=cortex-m4
+
+ifeq ($(FLOAT_TYPE), hard)
+#CFLAGS += -fsingle-precision-constant -Wdouble-promotion
+CFLAGS += -fsingle-precision-constant
+CFLAGS += -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D__FPU_PRESENT=1 -D__FPU_USED=1
+else
+CFLAGS += -msoft-float
+endif
+
+###################################################
+
+# Definitions for the STM32F4 Standard Peripheral Library
+
+PERIPHLIBVER = V1.1.0
+PERIPHLIBNAME = STM32F4xx_DSP_StdPeriph_Lib
+PERIPHLIBDIR = $(PERIPHLIBNAME)_$(PERIPHLIBVER)
+CMSIS = $(PERIPHLIBDIR)/Libraries/CMSIS
+STM32F4LIB = $(PERIPHLIBDIR)/Libraries/STM32F4xx_StdPeriph_Driver
+STM32F4TEMPLATE = $(PERIPHLIBDIR)/Project/STM32F4xx_StdPeriph_Templates
+DSPLIB = $(PERIPHLIBDIR)/Libraries/CMSIS/DSP_Lib
+
+CFLAGS += -DUSE_STDPERIPH_DRIVER -I$(STM32F4LIB)/inc -I$(STM32F4TEMPLATE)
+CFLAGS += -I$(CMSIS)/Include -I$(CMSIS)/Device/ST/STM32F4xx/Include
+CFLAGS += -DARM_MATH_CM4
+
+###################################################
+
+# Sources
+
+SRCS = main.c gdb_stdio.c stm32f4_timer.c system_stm32f4xx.c
+
+# Codec 2
+
+CODEC2_SRC=../src
+SRCS += \
+$(CODEC2_SRC)/lpc.c \
+$(CODEC2_SRC)/nlp.c \
+$(CODEC2_SRC)/postfilter.c \
+$(CODEC2_SRC)/sine.c \
+$(CODEC2_SRC)/codec2.c \
+$(CODEC2_SRC)/kiss_fft.c \
+$(CODEC2_SRC)/interp.c \
+$(CODEC2_SRC)/lsp.c \
+$(CODEC2_SRC)/phase.c \
+$(CODEC2_SRC)/quantise.c \
+$(CODEC2_SRC)/pack.c \
+$(CODEC2_SRC)/codebook.c \
+$(CODEC2_SRC)/codebookd.c \
+$(CODEC2_SRC)/codebookjvm.c \
+$(CODEC2_SRC)/codebookge.c \
+$(CODEC2_SRC)/dump.c
+
+CFLAGS += -D__EMBEDDED__ -DTIMER
+#CFLAGS += -DDUMP
+CFLAGS += -I/home/david/codec2-dev/src
+CFLAGS += -I/home/david/codec2-dev/unittest
+CFLAGS += -Iinc
+
+FFT_TEST_SRCS = \
+$(DSPLIB)/Examples/arm_fft_bin_example/arm_fft_bin_data.c \
+fft_test.c \
+src/startup_stm32f4xx.s \
+stm32f4_timer.c \
+gdb_stdio.c \
+../src/kiss_fft.c
+
+###################################################
+
+vpath %.c src
+vpath %.a lib
+
+ROOT=$(shell pwd)
+
+# Library paths
+
+LIBPATHS =
+
+# Libraries to link
+
+LIBS = libstm32f4.a -lg -lnosys -lm
+
+# startup file
+
+SRCS += src/startup_stm32f4xx.s
+
+OBJS = $(SRCS:.c=.o)
+
+###################################################
+
+all: libstm32f4.a $(PROJ_NAME).elf fft_test.elf
+
+libstm32f4.a:
+ $(MAKE) $(STM32F4TEMPLATE)/system_stm32f4xx.o
+ for F in $(STM32F4LIB)/src/*.c ; do $(MAKE) $${F%.c}.o ; done
+ for F in $(CMSIS)/DSP_Lib/Source/*/*.c ; do $(MAKE) $${F%.c}.o ; done
+ find $(PERIPHLIBDIR) -type f -name '*.o' -exec $(AR) crs libstm32f4.a {} ";"
+
+$(PROJ_NAME).elf: $(SRCS)
+ $(CC) $(CFLAGS) $^ -o $@ $(LIBPATHS) $(LIBS)
+
+fft_test.elf: $(FFT_TEST_SRCS)
+ $(CC) $(CFLAGS) $^ -o $@ $(LIBPATHS) $(LIBS)
+
+clean:
+ rm -f *.o
+ rm -f *.elf
+ rm -f libstm32f4.a
+ find $(PERIPHLIBDIR) -type f -name '*.o' -exec rm {} \;
--- /dev/null
+README.txt
+codec2-dev stm32f4
+David Rowe May 2013
+
+Getting Started
+-------------------------
+
+Describe what gdb_stdio does, describe what UT does. Where raw files
+end up. Dump files and how to use them.
+
+Install arm toolchain binary
+
+Download and untar STM32F4xx_DSP_StdPeriph_Lib_V1.1.0
+
+build codec2 unit test, describe what it does
+make
+
+1. Patching and build stlink:
+
+ TBC
+
+2. start st-util:
+
+ ~/stlink$ sudo ./st-util -f /home/david/codec2-dev/stm32/stm32f4_codec2.elf
+
+3. Start gdb:
+
+ ~/codec2-dev/stm32$ ~/sat/bin/arm-none-eabi-gdb stm32f4_codec2.elf
+
+ (gdb) tar ext :4242
+
+ (gdb) load
+ `/home/david/codec2-dev/stm32/fft_test.elf' has changed; re-reading symbols.
+ Loading section .isr_vector, size 0x188 lma 0x8000000
+ Loading section .text, size 0x1a4b4 lma 0x8000188
+ Loading section .data, size 0x28f0 lma 0x801a63c
+ Start address 0x800a885, load size 118572
+ Transfer rate: 13 KB/sec, 10779 bytes/write.
+
+4. Power cycle Discovery.
+
+5. ctrl-C to stop st-util, then restart st-util
+
+6. Back to gdb:
+
+ (gdb) tar ext :4242
+ A program is being debugged already. Kill it? (y or n) y
+ Remote connection closed
+ (gdb) tar ext :4242
+ Remote debugging using :4242
+ Reset_Handler () at lib/startup_stm32f4xx.s:69
+ 69 movs r1, #0
+
+ (gdb) c
+ Continuing.
+
+
+Process
+-------
+
+1. Profiling macros.
+
+2. enable DUMP to dump files, note proofiling times will be corrupted
+by this due to latency in talking to Host
+
+3. Compare outputs using octave/diff_codec. Worked example:
+
+diff_codec("~/stlink/ref/hts1a_out_1300.raw", "~/stlink/hts1a_out_1300.raw","~/stlink/stm32f4", "~/stlink/ref/stm32f4")
+
+
+Gotcha
+------
+
+using printf rather than gdb_stdio_printf, regular stdio functions are stubbed out so will link, just nothing will happen.
+
--- /dev/null
+/*---------------------------------------------------------------------------*\
+
+ FILE........: gdb_stdio.h
+ AUTHOR......: David Rowe
+ DATE CREATED: April 23 2013
+
+ Some stdio I/O functions that perform I/O on the host using gdb.
+
+\*---------------------------------------------------------------------------*/
+
+/*
+ Copyright (C) 2013 David Rowe
+
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License version 2.1, as
+ published by the Free Software Foundation. This program is
+ distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __GDB_STDIO__
+#define __GDB_STDIO__
+
+#include <stdio.h>
+#include <stdarg.h>
+
+void gdb_stdio_fprintf(FILE *file, const char *format, ...);
+void gdb_stdio_printf(const char *format, ...);
+FILE *gdb_stdio_fopen(char file_name[], char mode[]);
+void gdb_stdio_fclose(FILE *file);
+int gdb_stdio_fwrite(void *ptr, int size, int nmemb, FILE *file);
+int gdb_stdio_fread(void *ptr, int size, int nmemb, FILE *file);
+
+#endif
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_conf.h \r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 19-September-2011\r
+ * @brief Library configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_CONF_H\r
+#define __STM32F4xx_CONF_H\r
+\r
+#if defined (HSE_VALUE)\r
+/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */\r
+ #undef HSE_VALUE\r
+ #define HSE_VALUE ((uint32_t)8000000) \r
+#endif /* HSE_VALUE */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Uncomment the line below to enable peripheral header file inclusion */\r
+#include "stm32f4xx_adc.h"\r
+#include "stm32f4xx_can.h"\r
+#include "stm32f4xx_crc.h"\r
+#include "stm32f4xx_cryp.h"\r
+#include "stm32f4xx_dac.h"\r
+#include "stm32f4xx_dbgmcu.h"\r
+#include "stm32f4xx_dcmi.h"\r
+#include "stm32f4xx_dma.h"\r
+#include "stm32f4xx_exti.h"\r
+#include "stm32f4xx_flash.h"\r
+#include "stm32f4xx_fsmc.h"\r
+#include "stm32f4xx_hash.h"\r
+#include "stm32f4xx_gpio.h"\r
+#include "stm32f4xx_i2c.h"\r
+#include "stm32f4xx_iwdg.h"\r
+#include "stm32f4xx_pwr.h"\r
+#include "stm32f4xx_rcc.h"\r
+#include "stm32f4xx_rng.h"\r
+#include "stm32f4xx_rtc.h"\r
+#include "stm32f4xx_sdio.h"\r
+#include "stm32f4xx_spi.h"\r
+#include "stm32f4xx_syscfg.h"\r
+#include "stm32f4xx_tim.h"\r
+#include "stm32f4xx_usart.h"\r
+#include "stm32f4xx_wwdg.h"\r
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* If an external clock source is used, then the value of the following define \r
+ should be set to the value of the external clock source, else, if no external \r
+ clock is used, keep this define commented */\r
+/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */\r
+\r
+\r
+/* Uncomment the line below to expanse the "assert_param" macro in the \r
+ Standard Peripheral Library drivers code */\r
+/* #define USE_FULL_ASSERT 1 */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function\r
+ * which reports the name of the source file and the source\r
+ * line number of the call that failed. \r
+ * If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#endif /* __STM32F4xx_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* ---------------------------------------------------------------------- \r
+* Copyright (C) 2010 ARM Limited. All rights reserved. \r
+* \r
+* $Date: 29. November 2010 \r
+* $Revision: V1.0.3 \r
+* \r
+* Project: CMSIS DSP Library \r
+* Title: arm_fft_bin_example_f32.c \r
+* \r
+* Description: Example code demonstrating calculation of Max energy bin of \r
+* frequency domain of input signal. \r
+* \r
+* Target Processor: Cortex-M4/Cortex-M3 \r
+*\r
+*\r
+* Version 1.0.3 2010/11/29 \r
+* Re-organized the CMSIS folders and updated documentation. \r
+* \r
+* Version 1.0.1 2010/10/05 KK \r
+* Production release and review comments incorporated. \r
+*\r
+* Version 1.0.0 2010/09/20 KK\r
+* Production release and review comments incorporated.\r
+* ------------------------------------------------------------------- */ \r
+ \r
+/** \r
+ * @ingroup groupExamples \r
+ */ \r
+ \r
+/** \r
+ * @defgroup FrequencyBin Frequency Bin Example \r
+ * \r
+ * \par Description\r
+ * \par\r
+ * Demonstrates the calculation of the maximum energy bin in the frequency \r
+ * domain of the input signal with the use of Complex FFT, Complex \r
+ * Magnitude, and Maximum functions. \r
+ * \r
+ * \par Algorithm:\r
+ * \par\r
+ * The input test signal contains a 10 kHz signal with uniformly distributed white noise. \r
+ * Calculating the FFT of the input signal will give us the maximum energy of the \r
+ * bin corresponding to the input frequency of 10 kHz. \r
+ * \r
+ * \par Block Diagram:\r
+ * \image html FFTBin.gif "Block Diagram"\r
+ * \par\r
+ * The figure below shows the time domain signal of 10 kHz signal with \r
+ * uniformly distributed white noise, and the next figure shows the input\r
+ * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. \r
+ * \par\r
+ * \image html FFTBinInput.gif "Input signal in Time domain" \r
+ * \image html FFTBinOutput.gif "Input signal in Frequency domain"\r
+ *\r
+ * \par Variables Description:\r
+ * \par\r
+ * \li \c testInput_f32_10khz points to the input data\r
+ * \li \c testOutput points to the output data\r
+ * \li \c fftSize length of FFT\r
+ * \li \c ifftFlag flag for the selection of CFFT/CIFFT\r
+ * \li \c doBitReverse Flag for selection of normal order or bit reversed order\r
+ * \li \c refIndex reference index value at which maximum energy of bin ocuurs\r
+ * \li \c testIndex calculated index value at which maximum energy of bin ocuurs\r
+ * \r
+ * \par CMSIS DSP Software Library Functions Used:\r
+ * \par\r
+ * - arm_cfft_radix4_init_f32()\r
+ * - arm_cfft_radix4_f32()\r
+ * - arm_cmplx_mag_f32()\r
+ * - arm_max_f32()\r
+ *\r
+ * <b> Refer </b> \r
+ * \link arm_fft_bin_example_f32.c \endlink\r
+ * \r
+ */ \r
+ \r
+ \r
+/** \example arm_fft_bin_example_f32.c \r
+ */ \r
+\r
+ \r
+#include "arm_math.h" \r
+#include "gdb_stdio.h"\r
+#include "machdep.h"\r
+#include "kiss_fft.h"\r
+ \r
+#define TEST_LENGTH_SAMPLES 1024\r
+ \r
+/* ------------------------------------------------------------------- \r
+* External Input and Output buffer Declarations for FFT Bin Example \r
+* ------------------------------------------------------------------- */ \r
+extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; \r
+static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; \r
+static float32_t kiss_complex_out[TEST_LENGTH_SAMPLES]; \r
+ \r
+/* ------------------------------------------------------------------ \r
+* Global variables for FFT Bin Example \r
+* ------------------------------------------------------------------- */ \r
+uint32_t fftSize = TEST_LENGTH_SAMPLES/2; \r
+uint32_t ifftFlag = 0; \r
+uint32_t doBitReverse = 1; \r
+ \r
+/* Reference index at which max energy of bin ocuurs */ \r
+uint32_t refIndex = 213, testIndex = 0; \r
+ \r
+/* ---------------------------------------------------------------------- \r
+* Max magnitude FFT Bin test \r
+* ------------------------------------------------------------------- */ \r
+ \r
+void SystemInit(void);\r
+\r
+int main(void) \r
+{ \r
+ \r
+ arm_status status; \r
+ arm_cfft_radix2_instance_f32 S; \r
+ float32_t maxValue; \r
+ unsigned int fft_start, kiss_fft_start;\r
+ kiss_fft_cfg fft_fwd_cfg;\r
+\r
+ SystemInit();\r
+ machdep_timer_init();\r
+ fft_fwd_cfg = kiss_fft_alloc(fftSize, 0, NULL, NULL);\r
+ kiss_fft_start = machdep_timer_sample(); \r
+ kiss_fft(fft_fwd_cfg, (kiss_fft_cpx *)testInput_f32_10khz, \r
+ (kiss_fft_cpx *)kiss_complex_out);\r
+ machdep_timer_sample_and_log(kiss_fft_start, " kiss_fft"); \r
+ \r
+ status = ARM_MATH_SUCCESS; \r
+ \r
+ /* Initialize the CFFT/CIFFT module */ \r
+ status = arm_cfft_radix2_init_f32(&S, fftSize, ifftFlag, doBitReverse); \r
+\r
+ /* Process the data through the CFFT/CIFFT module */ \r
+ fft_start = machdep_timer_sample(); \r
+ arm_cfft_radix2_f32(&S, testInput_f32_10khz); \r
+ machdep_timer_sample_and_log(fft_start, " fft"); \r
+ machdep_timer_print_logged_samples();\r
+\r
+ /* Process the data through the Complex Magnitude Module for \r
+ calculating the magnitude at each bin */ \r
+ arm_cmplx_mag_f32(testInput_f32_10khz, testOutput,fftSize); \r
+ \r
+ /* Calculates maxValue and returns corresponding BIN value */ \r
+ arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); \r
+ \r
+ if(testIndex != refIndex) \r
+ { \r
+ status = ARM_MATH_TEST_FAILURE; \r
+ } \r
+ \r
+ /* ---------------------------------------------------------------------- \r
+ ** Loop here if the signals fail the PASS check. \r
+ ** This denotes a test failure \r
+ ** ------------------------------------------------------------------- */ \r
+ \r
+ if( status != ARM_MATH_SUCCESS) \r
+ { \r
+ while(1); \r
+ } \r
+\r
+ while(1); /* main function does not return */\r
+\r
+ return 0;\r
+} \r
+ \r
+ /** \endlink */ \r
+ \r
+ \r
+/*\r
+ * Dummy function to avoid compiler error\r
+ */\r
+void _init() { }\r
+\r
+\r
+ \r
--- /dev/null
+/*---------------------------------------------------------------------------*\
+
+ FILE........: gdb_stdio.c
+ AUTHOR......: David Rowe
+ DATE CREATED: April 23 2013
+
+ Some stdio I/O functions that perform I/O on the host using gdb.
+
+\*---------------------------------------------------------------------------*/
+
+/*
+ Copyright (C) 2013 David Rowe
+
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License version 2.1, as
+ published by the Free Software Foundation. This program is
+ distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <stdio.h>
+#include <string.h>
+#include <stdarg.h>
+#include "gdb_stdio.h"
+
+#define MAX_STR 2048
+
+/* command codes we use to signal host */
+
+#define GDB_STDIO_PRINTF 1
+#define GDB_STDIO_FOPEN 2
+#define GDB_STDIO_FCLOSE 3
+#define GDB_STDIO_FWRITE 4
+#define GDB_STDIO_FREAD 5
+#define GDB_STDIO_FPRINTF 6
+
+/* globals we use to communicate with host */
+
+volatile int gdb_stdio_func = 0;
+volatile int gdb_stdio_ret = 0;
+volatile char *gdb_stdio_pstr1;
+volatile char *gdb_stdio_pstr2;
+volatile int gdb_stdio_strlen1;
+volatile int gdb_stdio_strlen2;
+volatile FILE *gdb_stdio_file;
+volatile void *gdb_stdio_ptr;
+volatile int gdb_stdio_size;
+volatile int gdb_stdio_nmem;
+
+void gdb_stdio_fprintf(FILE *file, const char *format, ...) {
+ va_list arg;
+ char str[MAX_STR];
+
+ va_start(arg, format);
+ vsnprintf(str, MAX_STR, format, arg);
+ va_end(arg);
+ gdb_stdio_file = file;
+ gdb_stdio_pstr1 = str;
+ gdb_stdio_strlen1 = strlen(str);
+
+ gdb_stdio_func = GDB_STDIO_FPRINTF;
+ while(gdb_stdio_func);
+}
+
+void gdb_stdio_printf(const char *format, ...) {
+ va_list arg;
+ char str[MAX_STR];
+
+ va_start(arg, format);
+ vsnprintf(str, MAX_STR, format, arg);
+ va_end(arg);
+ gdb_stdio_pstr1 = str;
+ gdb_stdio_strlen1 = strlen(str);
+
+ gdb_stdio_func = GDB_STDIO_PRINTF;
+ while(gdb_stdio_func);
+}
+
+FILE *gdb_stdio_fopen(char file_name[], char mode[]) {
+ gdb_stdio_pstr1 = file_name;
+ gdb_stdio_pstr2 = mode;
+ gdb_stdio_strlen1 = strlen(file_name);
+ gdb_stdio_strlen2 = strlen(mode);
+
+ gdb_stdio_func = GDB_STDIO_FOPEN;
+ while(gdb_stdio_func);
+ return (FILE*)gdb_stdio_ret;
+}
+
+void gdb_stdio_fclose(FILE *file) {
+ gdb_stdio_file = file;
+
+ gdb_stdio_func = GDB_STDIO_FCLOSE;
+ while(gdb_stdio_func);
+}
+
+int gdb_stdio_fwrite(void *ptr, int size, int nmem, FILE *file) {
+ gdb_stdio_ptr = ptr;
+ gdb_stdio_size = size;
+ gdb_stdio_nmem = nmem;
+ gdb_stdio_file = file;
+
+ gdb_stdio_func = GDB_STDIO_FWRITE;
+ while(gdb_stdio_func);
+ return gdb_stdio_ret;
+}
+
+int gdb_stdio_fread(void *ptr, int size, int nmem, FILE *file) {
+ gdb_stdio_ptr = ptr;
+ gdb_stdio_size = size;
+ gdb_stdio_nmem = nmem;
+ gdb_stdio_file = file;
+
+ gdb_stdio_func = GDB_STDIO_FREAD;
+ while(gdb_stdio_func);
+ return gdb_stdio_ret;
+}
+
--- /dev/null
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include <math.h>\r
+\r
+#include "stm32f4xx_conf.h"\r
+#include "stm32f4xx.h"\r
+#include "gdb_stdio.h"\r
+#include "codec2.h"\r
+#include "dump.h"\r
+#include "sine.h"\r
+#include "machdep.h"\r
+\r
+#ifdef __EMBEDDED__\r
+#define printf gdb_stdio_printf\r
+#define fopen gdb_stdio_fopen\r
+#define fclose gdb_stdio_fclose\r
+#define fread gdb_stdio_fread\r
+#define fwrite gdb_stdio_fwrite\r
+#endif\r
+\r
+static void c2demo(int mode, char inputfile[], char outputfile[])\r
+{\r
+ struct CODEC2 *codec2;\r
+ short *inbuf, *outbuf;\r
+ unsigned char *bits;\r
+ int nsam, nbit;\r
+ FILE *fin, *fout;\r
+ int frame;\r
+ unsigned int enc_start, dec_start;\r
+\r
+ codec2 = codec2_create(mode);\r
+ nsam = codec2_samples_per_frame(codec2);\r
+ outbuf = (short*)malloc(nsam*sizeof(short));\r
+ inbuf = (short*)malloc(nsam*sizeof(short));\r
+ nbit = codec2_bits_per_frame(codec2);\r
+ bits = (unsigned char*)malloc(nbit*sizeof(char));\r
+\r
+ fin = fopen(inputfile, "rb");\r
+ if (fin == NULL) {\r
+ printf("Error opening input file: %s\n",inputfile);\r
+ exit(1);\r
+ }\r
+\r
+ fout = fopen(outputfile, "wb");\r
+ if (fout == NULL) {\r
+ printf("Error opening output file: %s\n",outputfile);\r
+ exit(1);\r
+ }\r
+\r
+ #ifdef DUMP\r
+ dump_on("stm32f4");\r
+ #endif\r
+ frame = 0;\r
+\r
+ while (fread(inbuf, sizeof(short), nsam, fin) == nsam) {\r
+ enc_start = machdep_timer_sample();\r
+ codec2_encode(codec2, bits, inbuf);\r
+ dec_start = machdep_timer_sample_and_log(enc_start, " enc"); \r
+ codec2_decode(codec2, outbuf, bits);\r
+ machdep_timer_sample_and_log(dec_start, " dec"); \r
+ fwrite((char*)outbuf, sizeof(short), nsam, fout);\r
+ printf("frame: %d\n", ++frame);\r
+ machdep_timer_print_logged_samples();\r
+ }\r
+\r
+ #ifdef DUMP\r
+ dump_off("sm32f4");\r
+ #endif\r
+\r
+ fclose(fin);\r
+ fclose(fout);\r
+ free(inbuf);\r
+ free(outbuf);\r
+ free(bits);\r
+ codec2_destroy(codec2);\r
+}\r
+\r
+int main(void) {\r
+ SystemInit();\r
+ printf("Starting\n");\r
+ machdep_timer_init ();\r
+\r
+ c2demo(CODEC2_MODE_1600, "hts1a.raw", "hts1a_out.raw");\r
+ printf("Finished\n");\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/*\r
+ * Dummy function to avoid compiler error\r
+ */\r
+void _init() {\r
+\r
+}\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f4xx.s\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 30-September-2011\r
+ * @brief STM32F4xx Devices vector table for Atollic TrueSTUDIO toolchain.\r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address\r
+ * - Configure the clock system and the external SRAM mounted on\r
+ * STM324xG-EVAL board to be used as data memory (optional,\r
+ * to be enabled by user)\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M4 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section.\r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */\r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called.\r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler:\r
+\r
+/* Copy the data segment initializers from flash to SRAM */\r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+\r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */\r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+\r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+\r
+/* Call the clock system intitialization function.*/\r
+ bl SystemInit\r
+/* Call static constructors */\r
+ bl __libc_init_array\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr\r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an\r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ * @param None\r
+ * @retval None\r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M3. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*\r
+*******************************************************************************/\r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+\r
+\r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+\r
+ /* External Interrupts */\r
+ .word WWDG_IRQHandler /* Window WatchDog */\r
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */\r
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */\r
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */\r
+ .word FLASH_IRQHandler /* FLASH */\r
+ .word RCC_IRQHandler /* RCC */\r
+ .word EXTI0_IRQHandler /* EXTI Line0 */\r
+ .word EXTI1_IRQHandler /* EXTI Line1 */\r
+ .word EXTI2_IRQHandler /* EXTI Line2 */\r
+ .word EXTI3_IRQHandler /* EXTI Line3 */\r
+ .word EXTI4_IRQHandler /* EXTI Line4 */\r
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */\r
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */\r
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */\r
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */\r
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */\r
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */\r
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */\r
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */\r
+ .word CAN1_TX_IRQHandler /* CAN1 TX */\r
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */\r
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */\r
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */\r
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */\r
+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */\r
+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */\r
+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */\r
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */\r
+ .word TIM2_IRQHandler /* TIM2 */\r
+ .word TIM3_IRQHandler /* TIM3 */\r
+ .word TIM4_IRQHandler /* TIM4 */\r
+ .word I2C1_EV_IRQHandler /* I2C1 Event */\r
+ .word I2C1_ER_IRQHandler /* I2C1 Error */\r
+ .word I2C2_EV_IRQHandler /* I2C2 Event */\r
+ .word I2C2_ER_IRQHandler /* I2C2 Error */\r
+ .word SPI1_IRQHandler /* SPI1 */\r
+ .word SPI2_IRQHandler /* SPI2 */\r
+ .word USART1_IRQHandler /* USART1 */\r
+ .word USART2_IRQHandler /* USART2 */\r
+ .word USART3_IRQHandler /* USART3 */\r
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */\r
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */\r
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */\r
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */\r
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */\r
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */\r
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */\r
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */\r
+ .word FSMC_IRQHandler /* FSMC */\r
+ .word SDIO_IRQHandler /* SDIO */\r
+ .word TIM5_IRQHandler /* TIM5 */\r
+ .word SPI3_IRQHandler /* SPI3 */\r
+ .word UART4_IRQHandler /* UART4 */\r
+ .word UART5_IRQHandler /* UART5 */\r
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */\r
+ .word TIM7_IRQHandler /* TIM7 */\r
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */\r
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */\r
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */\r
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */\r
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */\r
+ .word ETH_IRQHandler /* Ethernet */\r
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */\r
+ .word CAN2_TX_IRQHandler /* CAN2 TX */\r
+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */\r
+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */\r
+ .word CAN2_SCE_IRQHandler /* CAN2 SCE */\r
+ .word OTG_FS_IRQHandler /* USB OTG FS */\r
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */\r
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */\r
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */\r
+ .word USART6_IRQHandler /* USART6 */\r
+ .word I2C3_EV_IRQHandler /* I2C3 event */\r
+ .word I2C3_ER_IRQHandler /* I2C3 error */\r
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */\r
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */\r
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */\r
+ .word OTG_HS_IRQHandler /* USB OTG HS */\r
+ .word DCMI_IRQHandler /* DCMI */\r
+ .word CRYP_IRQHandler /* CRYP crypto */\r
+ .word HASH_RNG_IRQHandler /* Hash and Rng */\r
+ .word FPU_IRQHandler /* FPU */\r
+\r
+\r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler.\r
+* As they are weak aliases, any function with the same name will override\r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+\r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+\r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+\r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler\r
+\r
+ .weak WWDG_IRQHandler\r
+ .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+ .weak PVD_IRQHandler\r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+\r
+ .weak TAMP_STAMP_IRQHandler\r
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r
+\r
+ .weak RTC_WKUP_IRQHandler\r
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak FLASH_IRQHandler\r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+\r
+ .weak RCC_IRQHandler\r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI0_IRQHandler\r
+ .thumb_set EXTI0_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI1_IRQHandler\r
+ .thumb_set EXTI1_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI2_IRQHandler\r
+ .thumb_set EXTI2_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI3_IRQHandler\r
+ .thumb_set EXTI3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI4_IRQHandler\r
+ .thumb_set EXTI4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Stream0_IRQHandler\r
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Stream1_IRQHandler\r
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Stream2_IRQHandler\r
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Stream3_IRQHandler\r
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Stream4_IRQHandler\r
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Stream5_IRQHandler\r
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Stream6_IRQHandler\r
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\r
+\r
+ .weak ADC_IRQHandler\r
+ .thumb_set ADC_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_TX_IRQHandler\r
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_RX0_IRQHandler\r
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_RX1_IRQHandler\r
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_SCE_IRQHandler\r
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI9_5_IRQHandler\r
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_BRK_TIM9_IRQHandler\r
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_UP_TIM10_IRQHandler\r
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_TRG_COM_TIM11_IRQHandler\r
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_CC_IRQHandler\r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+\r
+ .weak TIM2_IRQHandler\r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+\r
+ .weak TIM3_IRQHandler\r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+\r
+ .weak TIM4_IRQHandler\r
+ .thumb_set TIM4_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_EV_IRQHandler\r
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_ER_IRQHandler\r
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_EV_IRQHandler\r
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_ER_IRQHandler\r
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
+\r
+ .weak SPI1_IRQHandler\r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+\r
+ .weak SPI2_IRQHandler\r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+\r
+ .weak USART1_IRQHandler\r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+\r
+ .weak USART2_IRQHandler\r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+\r
+ .weak USART3_IRQHandler\r
+ .thumb_set USART3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI15_10_IRQHandler\r
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+\r
+ .weak RTC_Alarm_IRQHandler\r
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
+\r
+ .weak OTG_FS_WKUP_IRQHandler\r
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak TIM8_BRK_TIM12_IRQHandler\r
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\r
+\r
+ .weak TIM8_UP_TIM13_IRQHandler\r
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\r
+\r
+ .weak TIM8_TRG_COM_TIM14_IRQHandler\r
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\r
+\r
+ .weak TIM8_CC_IRQHandler\r
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Stream7_IRQHandler\r
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\r
+\r
+ .weak FSMC_IRQHandler\r
+ .thumb_set FSMC_IRQHandler,Default_Handler\r
+\r
+ .weak SDIO_IRQHandler\r
+ .thumb_set SDIO_IRQHandler,Default_Handler\r
+\r
+ .weak TIM5_IRQHandler\r
+ .thumb_set TIM5_IRQHandler,Default_Handler\r
+\r
+ .weak SPI3_IRQHandler\r
+ .thumb_set SPI3_IRQHandler,Default_Handler\r
+\r
+ .weak UART4_IRQHandler\r
+ .thumb_set UART4_IRQHandler,Default_Handler\r
+\r
+ .weak UART5_IRQHandler\r
+ .thumb_set UART5_IRQHandler,Default_Handler\r
+\r
+ .weak TIM6_DAC_IRQHandler\r
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r
+\r
+ .weak TIM7_IRQHandler\r
+ .thumb_set TIM7_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Stream0_IRQHandler\r
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Stream1_IRQHandler\r
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Stream2_IRQHandler\r
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Stream3_IRQHandler\r
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Stream4_IRQHandler\r
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\r
+\r
+ .weak ETH_IRQHandler\r
+ .thumb_set ETH_IRQHandler,Default_Handler\r
+\r
+ .weak ETH_WKUP_IRQHandler\r
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_TX_IRQHandler\r
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_RX0_IRQHandler\r
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_RX1_IRQHandler\r
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_SCE_IRQHandler\r
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak OTG_FS_IRQHandler\r
+ .thumb_set OTG_FS_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Stream5_IRQHandler\r
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Stream6_IRQHandler\r
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Stream7_IRQHandler\r
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\r
+\r
+ .weak USART6_IRQHandler\r
+ .thumb_set USART6_IRQHandler,Default_Handler\r
+\r
+ .weak I2C3_EV_IRQHandler\r
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C3_ER_IRQHandler\r
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler\r
+\r
+ .weak OTG_HS_EP1_OUT_IRQHandler\r
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\r
+\r
+ .weak OTG_HS_EP1_IN_IRQHandler\r
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\r
+\r
+ .weak OTG_HS_WKUP_IRQHandler\r
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak OTG_HS_IRQHandler\r
+ .thumb_set OTG_HS_IRQHandler,Default_Handler\r
+\r
+ .weak DCMI_IRQHandler\r
+ .thumb_set DCMI_IRQHandler,Default_Handler\r
+\r
+ .weak CRYP_IRQHandler\r
+ .thumb_set CRYP_IRQHandler,Default_Handler\r
+\r
+ .weak HASH_RNG_IRQHandler\r
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler\r
+\r
+ .weak FPU_IRQHandler\r
+ .thumb_set FPU_IRQHandler,Default_Handler\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*---------------------------------------------------------------------------*\
+
+ FILE........: stm32f4_timer.c
+ AUTHOR......: David Rowe
+ DATE CREATED: May 2 2013
+
+ STM32F4 implementation of the machine dependant timer functions.
+
+\*---------------------------------------------------------------------------*/
+
+/*
+ Copyright (C) 2013 David Rowe
+
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License version 2.1, as
+ published by the Free Software Foundation. This program is
+ distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <string.h>
+#include "machdep.h"
+#include "gdb_stdio.h"
+
+volatile unsigned int *DWT_CYCCNT = (volatile unsigned int *)0xE0001004;
+volatile unsigned int *DWT_CONTROL = (volatile unsigned int *)0xE0001000;
+volatile unsigned int *SCB_DEMCR = (volatile unsigned int *)0xE000EDFC;
+
+#define CORE_CLOCK 168E6
+#define BUF_SZ 4096
+
+static char buf[BUF_SZ];
+
+void machdep_timer_init(void)
+{
+ static int enabled = 0;
+
+ if (!enabled) {
+ *SCB_DEMCR = *SCB_DEMCR | 0x01000000;
+ *DWT_CYCCNT = 0; // reset the counter
+ *DWT_CONTROL = *DWT_CONTROL | 1 ; // enable the counter
+
+ enabled = 1;
+ }
+ *buf = 0;
+}
+
+void machdep_timer_reset(void)
+{
+ *DWT_CYCCNT = 0; // reset the counter
+}
+
+unsigned int machdep_timer_sample(void) {
+ return *DWT_CYCCNT;
+}
+
+/* log to a buffer, we only call printf after timing finished as it is slow */
+
+unsigned int machdep_timer_sample_and_log(unsigned int start, char s[])
+{
+ char tmp[80];
+
+ unsigned int dwt = *DWT_CYCCNT - start;
+ sprintf(tmp, "%s %5.2f msecs\n",s,1000.0*(float)dwt/CORE_CLOCK);
+ if ((strlen(buf) + strlen(tmp)) < BUF_SZ)
+ strcat(buf, tmp);
+ return *DWT_CYCCNT;
+}
+
+void machdep_timer_print_logged_samples(void)
+{
+ gdb_stdio_printf("%s", buf);
+ *buf = 0;
+}
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f4xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.1\r
+ * @date 10-July-2012\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\r
+ * This file contains the system clock configuration for STM32F4xx devices,\r
+ * and is generated by the clock configuration tool\r
+ * stm32f4xx_Clock_Configuration_V1.0.1.xls\r
+ *\r
+ * 1. This file provides two functions and one global variable to be called from\r
+ * user application:\r
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
+ * and Divider factors, AHB/APBx prescalers and Flash settings),\r
+ * depending on the configuration made in the clock xls tool.\r
+ * This function is called at startup just after reset and\r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f4xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick\r
+ * timer or configure other parameters.\r
+ *\r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ * 2. After each device reset the HSI (16 MHz) is used as system clock source.\r
+ * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to\r
+ * configure the system clock before to branch to main program.\r
+ *\r
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
+ * function will do nothing and HSI still used as system clock source. User can\r
+ * add some code to deal with this issue inside the SetSysClock() function.\r
+ *\r
+ * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define\r
+ * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or\r
+ * through PLL, and you are using different crystal you have to adapt the HSE\r
+ * value to your own configuration.\r
+ *\r
+ * 5. This file configures the system clock as follows:\r
+ *=============================================================================\r
+ *=============================================================================\r
+ * Supported STM32F4xx device revision | Rev A\r
+ *-----------------------------------------------------------------------------\r
+ * System Clock source | PLL (HSE)\r
+ *-----------------------------------------------------------------------------\r
+ * SYSCLK(Hz) | 168000000\r
+ *-----------------------------------------------------------------------------\r
+ * HCLK(Hz) | 168000000\r
+ *-----------------------------------------------------------------------------\r
+ * AHB Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * APB1 Prescaler | 4\r
+ *-----------------------------------------------------------------------------\r
+ * APB2 Prescaler | 2\r
+ *-----------------------------------------------------------------------------\r
+ * HSE Frequency(Hz) | 8000000\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_M | 8\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_N | 336\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_P | 2\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_Q | 7\r
+ *-----------------------------------------------------------------------------\r
+ * PLLI2S_N | 352\r
+ *-----------------------------------------------------------------------------\r
+ * PLLI2S_R | 2\r
+ *-----------------------------------------------------------------------------\r
+ * I2S input clock(Hz) | 176000000\r
+ * |\r
+ * To achieve the following I2S config: |\r
+ * - Master clock output (MCKO): OFF |\r
+ * - Frame wide : 16bit |\r
+ * - Error % : 0,0000 |\r
+ * - Prescaler Odd factor (ODD): 1 |\r
+ * - Linear prescaler (DIV) : 14 |\r
+ *-----------------------------------------------------------------------------\r
+ * VDD(V) | 3,3\r
+ *-----------------------------------------------------------------------------\r
+ * Main regulator output voltage | Scale1 mode\r
+ *-----------------------------------------------------------------------------\r
+ * Flash Latency(WS) | 5\r
+ *-----------------------------------------------------------------------------\r
+ * Prefetch Buffer | OFF\r
+ *-----------------------------------------------------------------------------\r
+ * Instruction cache | ON\r
+ *-----------------------------------------------------------------------------\r
+ * Data cache | ON\r
+ *-----------------------------------------------------------------------------\r
+ * Require 48MHz for USB OTG FS, | Enabled\r
+ * SDIO and RNG clock |\r
+ *-----------------------------------------------------------------------------\r
+ *=============================================================================\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f4xx_system\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f4xx.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+/*!< Uncomment the following line if you need to use external SRAM mounted\r
+ on STM324xG_EVAL board as data memory */\r
+/* #define DATA_IN_ExtSRAM */\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/************************* PLL Parameters *************************************/\r
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */\r
+#define PLL_M 8\r
+#define PLL_N 336\r
+\r
+/* SYSCLK = PLL_VCO / PLL_P */\r
+#define PLL_P 2\r
+\r
+/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */\r
+#define PLL_Q 7\r
+\r
+/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N\r
+ I2SCLK = PLLI2S_VCO / PLLI2S_R */\r
+#define START_I2SCLOCK 0\r
+#define PLLI2S_N 352\r
+#define PLLI2S_R 2\r
+\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+uint32_t SystemCoreClock = 168000000;\r
+\r
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+#ifdef DATA_IN_ExtSRAM\r
+static void SystemInit_ExtMemCtl(void);\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the\r
+ * SystemFrequency variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+#endif\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+#ifdef DATA_IN_ExtSRAM\r
+ SystemInit_ExtMemCtl();\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+ /* Configure the System clock source, PLL Multiplier and Divider factors,\r
+ AHB/APBx prescalers and Flash settings ----------------------------------*/\r
+ SetSysClock();\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ *\r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect.\r
+ *\r
+ * @note - The system frequency computed by this function is not the real\r
+ * frequency in the chip. It is calculated based on the predefined\r
+ * constant and the selected clock source:\r
+ *\r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ *\r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ *\r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ *\r
+ * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ *\r
+ * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ *\r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ *\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */\r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+\r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,\r
+ * AHB/APBx prescalers and Flash settings\r
+ * @Note This function should be called only once the RCC clock configuration\r
+ * is reset to the default reset state (done in SystemInit() function).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+ /******************************************************************************/\r
+ /* PLL (clocked by HSE) used as System clock source */\r
+ /******************************************************************************/\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+ /* Enable HSE */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++;\r
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ }\r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */\r
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+ PWR->CR |= PWR_CR_VOS;\r
+\r
+ /* HCLK = SYSCLK / 1*/\r
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;\r
+\r
+ /* PCLK2 = HCLK / 2*/\r
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;\r
+\r
+ /* PCLK1 = HCLK / 4*/\r
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;\r
+\r
+ /* Configure the main PLL */\r
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |\r
+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);\r
+\r
+ /* Enable the main PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till the main PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */\r
+ FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;\r
+\r
+ /* Select the main PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= RCC_CFGR_SW_PLL;\r
+\r
+ /* Wait till the main PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock\r
+ configuration. User can add here some code to deal with this error */\r
+ }\r
+\r
+\r
+ /******************************************************************************/\r
+ /* I2S clock configuration */\r
+ /******************************************************************************/\r
+\r
+#if START_I2SCLOCK\r
+ /* PLLI2S clock used as I2S clock source */\r
+ RCC->CFGR &= ~RCC_CFGR_I2SSRC;\r
+\r
+ /* Configure PLLI2S */\r
+ RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);\r
+\r
+ /* Enable PLLI2S */\r
+ RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);\r
+\r
+ /* Wait till PLLI2S is ready */\r
+ while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)\r
+ {\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Setup the external memory controller. Called in startup_stm32f4xx.s\r
+ * before jump to __main\r
+ * @param None\r
+ * @retval None\r
+ */\r
+#ifdef DATA_IN_ExtSRAM\r
+/**\r
+ * @brief Setup the external memory controller.\r
+ * Called in startup_stm32f4xx.s before jump to main.\r
+ * This function configures the external SRAM mounted on STM324xG_EVAL board\r
+ * This SRAM will be used as program data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit_ExtMemCtl(void)\r
+{\r
+ /*-- GPIOs Configuration -----------------------------------------------------*/\r
+ /*\r
+ +-------------------+--------------------+------------------+------------------+\r
+ + SRAM pins assignment +\r
+ +-------------------+--------------------+------------------+------------------+\r
+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | \r
+ | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | \r
+ | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | \r
+ | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | \r
+ | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | \r
+ | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | \r
+ | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | \r
+ | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+\r
+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | \r
+ | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | \r
+ | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+\r
+ | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |\r
+ | | PE15 <-> FSMC_D12 |\r
+ +-------------------+--------------------+\r
+ */\r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r
+ RCC->AHB1ENR = 0x00000078;\r
+\r
+ /* Connect PDx pins to FSMC Alternate function */\r
+ GPIOD->AFR[0] = 0x00cc00cc;\r
+ GPIOD->AFR[1] = 0xcc0ccccc;\r
+ /* Configure PDx pins in Alternate function mode */\r
+ GPIOD->MODER = 0xaaaa0a0a;\r
+ /* Configure PDx pins speed to 100 MHz */\r
+ GPIOD->OSPEEDR = 0xffff0f0f;\r
+ /* Configure PDx pins Output type to push-pull */\r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */\r
+ GPIOD->PUPDR = 0x00000000;\r
+\r
+ /* Connect PEx pins to FSMC Alternate function */\r
+ GPIOE->AFR[0] = 0xc00cc0cc;\r
+ GPIOE->AFR[1] = 0xcccccccc;\r
+ /* Configure PEx pins in Alternate function mode */\r
+ GPIOE->MODER = 0xaaaa828a;\r
+ /* Configure PEx pins speed to 100 MHz */\r
+ GPIOE->OSPEEDR = 0xffffc3cf;\r
+ /* Configure PEx pins Output type to push-pull */\r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */\r
+ GPIOE->PUPDR = 0x00000000;\r
+\r
+ /* Connect PFx pins to FSMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00cccccc;\r
+ GPIOF->AFR[1] = 0xcccc0000;\r
+ /* Configure PFx pins in Alternate function mode */\r
+ GPIOF->MODER = 0xaa000aaa;\r
+ /* Configure PFx pins speed to 100 MHz */\r
+ GPIOF->OSPEEDR = 0xff000fff;\r
+ /* Configure PFx pins Output type to push-pull */\r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */\r
+ GPIOF->PUPDR = 0x00000000;\r
+\r
+ /* Connect PGx pins to FSMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00cccccc;\r
+ GPIOG->AFR[1] = 0x000000c0;\r
+ /* Configure PGx pins in Alternate function mode */\r
+ GPIOG->MODER = 0x00080aaa;\r
+ /* Configure PGx pins speed to 100 MHz */\r
+ GPIOG->OSPEEDR = 0x000c0fff;\r
+ /* Configure PGx pins Output type to push-pull */\r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */\r
+ GPIOG->PUPDR = 0x00000000;\r
+\r
+ /*-- FSMC Configuration ------------------------------------------------------*/\r
+ /* Enable the FSMC interface clock */\r
+ RCC->AHB3ENR = 0x00000001;\r
+\r
+ /* Configure and enable Bank1_SRAM2 */\r
+ FSMC_Bank1->BTCR[2] = 0x00001015;\r
+ FSMC_Bank1->BTCR[3] = 0x00010603;\r
+ FSMC_Bank1E->BWTR[2] = 0x0fffffff;\r
+ /*\r
+ Bank1_SRAM2 is configured as follow:\r
+\r
+ p.FSMC_AddressSetupTime = 3;\r
+ p.FSMC_AddressHoldTime = 0;\r
+ p.FSMC_DataSetupTime = 6;\r
+ p.FSMC_BusTurnAroundDuration = 1;\r
+ p.FSMC_CLKDivision = 0;\r
+ p.FSMC_DataLatency = 0;\r
+ p.FSMC_AccessMode = FSMC_AccessMode_A;\r
+\r
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;\r
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;\r
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; \r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;\r
+ */\r
+}\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000; /* end of 128K RAM on AHB bus*/
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+}
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector))
+ . = ALIGN(4);
+ } >FLASH
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ _exit = .;
+ } >FLASH
+
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array*))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = .;
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+}
--- /dev/null
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000; /* end of 128K RAM on AHB bus*/
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+}
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector))
+ . = ALIGN(4);
+ } >RAM
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ _exit = .;
+ } >RAM
+
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >RAM
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >RAM
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >RAM
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array*))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >RAM
+
+ /* used by the startup to initialize data */
+ _sidata = .;
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+}
projects / freetel-svn-tracking.git / commitdiff