dac driver now scales to DAC limits with buffer enabled, variable size dac FIFOs...

git-svn-id: https://svn.code.sf.net/p/freetel/code@1787 01035d8c-6547-0410-b346-abe4f91aad63

diff --git a/codec2-dev/stm32/inc/stm32f4_dac.h b/codec2-dev/stm32/inc/stm32f4_dac.h
index 9950f36a3b346f85d839d18430968b71e17caa08..d0b825927d4370bc09ca7e764af30e63fa852fa1 100644 (file)
--- a/codec2-dev/stm32/inc/stm32f4_dac.h
+++ b/codec2-dev/stm32/inc/stm32f4_dac.h
@@ -28,7 +28,9 @@
 #ifndef __STM32F4_DAC__
 #define __STM32F4_DAC__
 
-void dac_open(void);
+#define DAC_BUF_SZ   320
+
+void dac_open(int fifo_sz);
 int dac1_write(short buf[], int n); /* DAC1 pin PA4 */
 int dac2_write(short buf[], int n); /* DAC2 pin PA5 */
 

diff --git a/codec2-dev/stm32/src/dac_play.c b/codec2-dev/stm32/src/dac_play.c
index afed3f8cc7c3c8b8a206775f796c34f40c435969..a8a1565f864b26061a0cc01232f3f085193d13ea 100644 (file)
--- a/codec2-dev/stm32/src/dac_play.c
+++ b/codec2-dev/stm32/src/dac_play.c
@@ -29,13 +29,13 @@
 #include "stm32f4_dac.h"\r
 #include "gdb_stdio.h"\r
 \r
-#define N   2000\r
+#define N    (5*DAC_BUF_SZ)\r
 \r
 int main(void) {\r
     short  buf[N];\r
     FILE  *fplay;\r
 \r
-    dac_open();\r
+    dac_open(2*N);\r
 \r
     while(1) {\r
         fplay = fopen("stm_in.raw", "rb");\r

diff --git a/codec2-dev/stm32/src/dac_ut.c b/codec2-dev/stm32/src/dac_ut.c
index 039c6da388fc3882c69ec3b7e1cc1ecbde5085a3..40b13a44fd9e6d57682491077e11dae324be3a11 100644 (file)
--- a/codec2-dev/stm32/src/dac_ut.c
+++ b/codec2-dev/stm32/src/dac_ut.c
@@ -44,7 +44,7 @@ short aSine[] = {
 };\r
 \r
 int main(void) {\r
-    dac_open();\r
+    dac_open(4*DAC_BUF_SZ);\r
 \r
     while (1) {\r
 \r

diff --git a/codec2-dev/stm32/src/power_ut.c b/codec2-dev/stm32/src/power_ut.c
index a42286ea49cc137c9839deed673b3b114d85b643..416fc956e363a426850b4d967cb95f839e52916f 100644 (file)
--- a/codec2-dev/stm32/src/power_ut.c
+++ b/codec2-dev/stm32/src/power_ut.c
@@ -122,7 +122,7 @@ int main(int argc, char *argv[]) {
     gpio_init();\r
     machdep_timer_init ();\r
     adc_open();\r
-    dac_open();\r
+    dac_open(4*DAC_BUF_SZ);\r
 \r
     printf("Starting power_ut\n");\r
 \r

diff --git a/codec2-dev/stm32/src/sm1000_main.c b/codec2-dev/stm32/src/sm1000_main.c
index 90c926c8866d91a5d48f74b667cc73f1a69c14db..ed930fdd163f0eaf9dfd4319f35ed0a6813c614c 100644 (file)
--- a/codec2-dev/stm32/src/sm1000_main.c
+++ b/codec2-dev/stm32/src/sm1000_main.c
@@ -38,7 +38,7 @@ int main(void) {
     /* init all the drivers for various peripherals */\r
 \r
     sm1000_leds_switches_init();\r
-    dac_open();\r
+    dac_open(4*DAC_BUF_SZ);\r
     adc_open();\r
     f = freedv_open(FREEDV_MODE_1600);\r
 \r

diff --git a/codec2-dev/stm32/src/stm32f4_dac.c b/codec2-dev/stm32/src/stm32f4_dac.c
index 31fa7348f3b48034637eb6d51dcdf59cd625e6b9..3f0d520c766e8d0c83be14ea0392b845d7e1c04f 100644 (file)
--- a/codec2-dev/stm32/src/stm32f4_dac.c
+++ b/codec2-dev/stm32/src/stm32f4_dac.c
@@ -35,13 +35,19 @@
 /* write to these registers for 12 bit left aligned data, as per data sheet \r
    make sure 4 least sig bits set to 0 */\r
 \r
-#define DAC_DHR12L1_ADDRESS    0x4000740c\r
-#define DAC_DHR12L2_ADDRESS    0x40007418\r
+#define DAC_DHR12R1_ADDRESS    0x40007408\r
+#define DAC_DHR12R2_ADDRESS    0x40007414\r
 \r
-#define DAC_BUF_SZ   320\r
-#define FIFO_SZ      4*DAC_BUF_SZ\r
 #define DAC_MAX      4096            /* maximum amplitude */\r
 \r
+/* y=mx+c mapping of samples16 bit shorts to DAC samples.  Table: 74\r
+   of data sheet indicates With DAC buffer on, DAC range is limited to\r
+   0x0E0 to 0xF1C at VREF+ = 3.6 V, we have Vref=3.3V which is close.\r
+ */\r
+\r
+#define M ((3868.0-224.0)/65536.0)\r
+#define C 2047.0\r
+\r
 static struct FIFO *dac1_fifo;\r
 static struct FIFO *dac2_fifo;\r
 \r
@@ -54,15 +60,15 @@ static void dac2_config(void);
 \r
 int dac_underflow;\r
 \r
-void dac_open(void) {\r
+void dac_open(int fifo_size) {\r
 \r
     memset(dac1_buf, 32768, sizeof(short)*DAC_BUF_SZ);\r
     memset(dac2_buf, 32768, sizeof(short)*DAC_BUF_SZ);\r
 \r
     /* Create fifos */\r
 \r
-    dac1_fifo = fifo_create(FIFO_SZ);\r
-    dac2_fifo = fifo_create(FIFO_SZ);\r
+    dac1_fifo = fifo_create(fifo_size);\r
+    dac2_fifo = fifo_create(fifo_size);\r
     assert(dac1_fifo != NULL);\r
     assert(dac2_fifo != NULL);\r
 \r
@@ -155,7 +161,7 @@ static void dac1_config(void)
 \r
   DMA_DeInit(DMA1_Stream5);\r
   DMA_InitStructure.DMA_Channel = DMA_Channel_7;  \r
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12L1_ADDRESS;\r
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12R1_ADDRESS;\r
   DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dac1_buf;\r
   DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;\r
   DMA_InitStructure.DMA_BufferSize = DAC_BUF_SZ;\r
@@ -213,7 +219,7 @@ static void dac2_config(void)
 \r
   DMA_DeInit(DMA1_Stream6);\r
   DMA_InitStructure.DMA_Channel = DMA_Channel_7;  \r
-  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12L2_ADDRESS;\r
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12R2_ADDRESS;\r
   DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dac2_buf;\r
   DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;\r
   DMA_InitStructure.DMA_BufferSize = DAC_BUF_SZ;\r
@@ -266,7 +272,7 @@ static void dac2_config(void)
 */\r
 \r
 void DMA1_Stream5_IRQHandler(void) {\r
-    int i, sam;\r
+    int i, j, sam;\r
     short signed_buf[DAC_BUF_SZ/2];\r
 \r
     /* Transfer half empty interrupt - refill first half */\r
@@ -282,8 +288,8 @@ void DMA1_Stream5_IRQHandler(void) {
         /* convert to unsigned */\r
 \r
         for(i=0; i<DAC_BUF_SZ/2; i++) {\r
-            sam = (int)signed_buf[i] + 32768;\r
-            dac1_buf[i] = (unsigned short)(sam & 0xfff000);\r
+            sam = (int)(M*(float)signed_buf[i] + C);\r
+            dac1_buf[i] = (unsigned short)sam;\r
         }\r
 \r
         /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
@@ -303,9 +309,9 @@ void DMA1_Stream5_IRQHandler(void) {
 \r
         /* convert to unsigned */\r
 \r
-        for(i=0; i<DAC_BUF_SZ/2; i++) {\r
-            sam = (int)signed_buf[i] + 32768;\r
-            dac1_buf[i+DAC_BUF_SZ/2] = (unsigned short)(sam & 0xfff000);\r
+        for(i=0, j=DAC_BUF_SZ/2; i<DAC_BUF_SZ/2; i++,j++) {\r
+            sam = (int)(M*(float)signed_buf[i] + C);\r
+            dac1_buf[j] = (unsigned short)sam;\r
         }\r
 \r
         /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
@@ -319,7 +325,7 @@ void DMA1_Stream5_IRQHandler(void) {
 */\r
 \r
 void DMA1_Stream6_IRQHandler(void) {\r
-    int i, sam;\r
+    int i, j, sam;\r
     short signed_buf[DAC_BUF_SZ/2];\r
 \r
     /* Transfer half empty interrupt - refill first half */\r
@@ -335,8 +341,8 @@ void DMA1_Stream6_IRQHandler(void) {
         /* convert to unsigned */\r
 \r
         for(i=0; i<DAC_BUF_SZ/2; i++) {\r
-            sam = (int)signed_buf[i] + 32768;\r
-            dac2_buf[i] = (unsigned short)(sam & 0xfff000);\r
+            sam = (int)(M*(float)signed_buf[i] + C);\r
+            dac2_buf[i] = (unsigned short)sam;\r
         }\r
 \r
         /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
@@ -356,9 +362,9 @@ void DMA1_Stream6_IRQHandler(void) {
 \r
         /* convert to unsigned  */\r
 \r
-        for(i=0; i<DAC_BUF_SZ/2; i++) {\r
-            sam = (int)signed_buf[i] + 32768;\r
-            dac2_buf[i+DAC_BUF_SZ/2] = (unsigned short)(sam & 0xfff000);\r
+        for(i=0, j=DAC_BUF_SZ/2; i<DAC_BUF_SZ/2; i++,j++) {\r
+            sam = (int)(M*(float)signed_buf[i] + C);\r
+            dac2_buf[j] = (unsigned short)sam;\r
         }\r
 \r
         /* Clear DMA Stream Transfer Complete interrupt pending bit */\r