updated power budget calcs

git-svn-id: https://svn.code.sf.net/p/freetel/code@2578 01035d8c-6547-0410-b346-abe4f91aad63

diff --git a/sm2000/doc/sm202 Task List.txt b/sm2000/doc/sm202 Task List.txt
index aa8824aca8373c2127e73c87bf8e37272955f69a..e5cf499f0ca6450152b5a1ba1667cb499ec92d7f 100644 (file)
--- a/sm2000/doc/sm202 Task List.txt
+++ b/sm2000/doc/sm202 Task List.txt
@@ -190,10 +190,11 @@ Task List
         + if not good enough we'll need an external ADC\r
         + test against two tone, MDS and ACR\r
         + Result: met 135dBm spec on prototype so OK\r
-    [ ] Power dissipation of active devices and resistors\r
+    [X] Power dissipation of active devices and resistors\r
         + easy to exceed limits in SM resistors and transistors\r
         + RF drivers draw lots of current\r
         + mitigation: power spereadhseet in doc section\r
+        + looks good, see also email to Rick 28/12/15 sub: "sm205 powr budget"\r
     [X] IF termination of 1st mixer\r
         + how to test if this is OK -> Sweep with R/L bridge\r
     [X] do we need a way to bypass the LNA?\r
@@ -258,6 +259,9 @@ Task List
     [ ] how to connect SCA/SCL on clock chips to uC?\r
         + is there a separate enable?\r
     [ ] LEDs for control signals/rails\r
+    [ ] Add a Av=2 op-amp to take 3v3 DAC max from uC to 5V\r
+        max for Vgg driving PA final Q14.  Will need to be powered by 5V rail.\r
+        This is a preacuation in case we need > 3V for some FETs\r
 \r
 [ ] Rev A PCB Layout\r
     [ ] footprints for all devices\r

diff --git a/sm2000/doc/sm205_power_budget.xls b/sm2000/doc/sm205_power_budget.xls
index f4bcf0babc282a9b972be8963b0d95a125fa5e53..e9d6bb89d957ac53f3eba88e3f75b6b8ae6a5a3d 100644 (file)
Binary files a/sm2000/doc/sm205_power_budget.xls and b/sm2000/doc/sm205_power_budget.xls differ