###################################################
-all: libstm32f4.a $(PROJ_NAME).elf fft_test.elf dac_ut.elf
+all: libstm32f4.a $(PROJ_NAME).elf fft_test.elf dac_ut.elf dac_play.elf
dl/$(PERIPHLIBZIP):
mkdir -p dl
fft_test.elf: $(FFT_TEST_SRCS)
$(CC) $(CFLAGS) $^ -o $@ $(LIBPATHS) $(LIBS)
-DAC_TEST_SRCS=\
+DAC_UT_SRCS=\
src/dac_ut.c \
-src/dac_it.c \
+../src/fifo.c \
+src/stm32f4_dac.c \
src/system_stm32f4xx.c \
src/startup_stm32f4xx.s \
src/init.c
-dac_ut.elf: $(DAC_TEST_SRCS)
+dac_ut.elf: $(DAC_UT_SRCS)
+ $(CC) $(CFLAGS) -O0 $^ -o $@ $(LIBPATHS) $(LIBS)
+
+DAC_PLAY_SRCS=\
+src/dac_play.c \
+../src/fifo.c \
+gdb_stdio.c \
+src/stm32f4_dac.c \
+src/system_stm32f4xx.c \
+src/startup_stm32f4xx.s \
+src/init.c
+
+dac_play.elf: $(DAC_PLAY_SRCS)
$(CC) $(CFLAGS) -O0 $^ -o $@ $(LIBPATHS) $(LIBS)
clean:
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file DMA/DMA_FLASHToRAM/stm32f4xx_it.h \r
- * @author MCD Application Team\r
- * @version V1.1.0\r
- * @date 18-January-2013\r
- * @brief This file contains the headers of the interrupt handlers.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F4xx_IT_H\r
-#define __STM32F4xx_IT_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f4xx_dma.h"\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-/* Exported macro ------------------------------------------------------------*/\r
-/* Exported functions ------------------------------------------------------- */\r
-\r
-void NMI_Handler(void);\r
-void HardFault_Handler(void);\r
-void MemManage_Handler(void);\r
-void BusFault_Handler(void);\r
-void UsageFault_Handler(void);\r
-void SVC_Handler(void);\r
-void DebugMon_Handler(void);\r
-void PendSV_Handler(void);\r
-void SysTick_Handler(void);\r
-void DMA_STREAM_IRQHANDLER(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F4xx_IT_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*---------------------------------------------------------------------------*\
+
+ FILE........: stm32f4_dac.h
+ AUTHOR......: David Rowe
+ DATE CREATED: 1 June 2013
+
+ DAC driver module for STM32F4.
+
+\*---------------------------------------------------------------------------*/
+
+/*
+ Copyright (C) 2013 David Rowe
+
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License version 2.1, as
+ published by the Free Software Foundation. This program is
+ distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __STM32F4_DAC__
+#define __STM32F4_DAC__
+
+void dac_open(void);
+int dac_write(short buf[], int n);
+
+#endif
/* STM32F4xx Peripherals Interrupt Handlers */\r
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r
/* available peripheral interrupt handler's name please refer to the startup */\r
-/* file (startup_stm32f40xx.s/startup_stm32f427x.s). */\r
+/* file (startup_stm32f40xx.s/startup_stm32f427x.s). */\r
/******************************************************************************/\r
\r
/**\r
*/\r
void DMA1_Stream6_IRQHandler(void)\r
{\r
- /* Test on DMA Stream Transfer Complete interrupt */\r
- if(DMA_GetITStatus(DMA1_Stream6, DMA_IT_HTIF6))\r
+\r
+ /* Transfer half empty interrupt */\r
+\r
+ if(DMA_GetITStatus(DMA1_Stream6, DMA_IT_HTIF6) != RESET))\r
{\r
- /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
- DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_HTIF6); \r
- interrupts++;\r
+ /* fill first half from fifo */\r
+\r
+ fifo_read(DMA1_Stream6_fifo, dac_buf, DAC_BUF_SZ/2);\r
+\r
+ /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
+\r
+ DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_HTIF6); \r
+\r
+ interrupts++;\r
}\r
- if(DMA_GetITStatus(DMA1_Stream6, DMA_IT_TCIF6))\r
+\r
+ /* Transfer complete interrupt */\r
+\r
+ if(DMA_GetITStatus(DMA1_Stream6, DMA_IT_TCIF6) != RESET))\r
{\r
- /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
- DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_TCIF6); \r
- interrupts++;\r
+ /* fill second half from fifo */\r
+\r
+ fifo_read(DMA1_Stream6_fifo, &dac_buf[DAC_BUF_SZ/2], DAC_BUF_SZ/2);\r
+\r
+ /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
+\r
+ DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_TCIF6); \r
+\r
+ interrupts++;\r
}\r
}\r
\r
--- /dev/null
+/*---------------------------------------------------------------------------*\\r
+\r
+ FILE........: dac_play.c\r
+ AUTHOR......: David Rowe\r
+ DATE CREATED: 1 June 2013\r
+\r
+ Plays a 16 kHz sample rate raw file to the Discovery DAC.\r
+\r
+\*---------------------------------------------------------------------------*/\r
+\r
+/*\r
+ Copyright (C) 2013 David Rowe\r
+\r
+ All rights reserved.\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU Lesser General Public License version 2.1, as\r
+ published by the Free Software Foundation. This program is\r
+ distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
+ License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public License\r
+ along with this program; if not, see <http://www.gnu.org/licenses/>.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include "stm32f4_dac.h"\r
+#include "gdb_stdio.h"\r
+\r
+#define printf gdb_stdio_printf\r
+#define fopen gdb_stdio_fopen\r
+#define fclose gdb_stdio_fclose\r
+#define fread gdb_stdio_fread\r
+#define fwrite gdb_stdio_fwrite\r
+\r
+#define N1 24000\r
+#define N2 320\r
+\r
+int main(void) {\r
+ short *buf, *pbuf;\r
+ FILE *fin;\r
+ int i, nframes;\r
+\r
+ buf = (short*)malloc(N1*sizeof(short));\r
+ dac_open();\r
+\r
+ fin = fopen("stm_in.raw", "rb");\r
+ if (fin == NULL) {\r
+ printf("Error opening input file: stm_in.raw\n\nTerminating....\n");\r
+ exit(1);\r
+ }\r
+ fread(buf, sizeof(short), N1, fin);\r
+ fclose(fin);\r
+\r
+ nframes = N1/N2;\r
+ while(1) {\r
+ printf("Starting!\n");\r
+ pbuf = buf;\r
+ for(i=0; i<nframes; i++) {\r
+ while(dac_write(pbuf, N2) == -1);\r
+ pbuf += N2;\r
+ } \r
+ printf("Finished!\n");\r
+ }\r
+}\r
+\r
along with this program; if not, see <http://www.gnu.org/licenses/>.\r
*/\r
\r
+#include <assert.h>\r
+#include "stm32f4_dac.h"\r
\r
-/* Modfied version of the following: */\r
-\r
-/**\r
- ******************************************************************************\r
- * @file DAC/DAC_SignalsGeneration/main.c \r
- * @author MCD Application Team\r
- * @version V1.1.0\r
- * @date 18-January-2013\r
- * @brief Main program body.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-#include "stm32f4xx.h"\r
-\r
-#define DAC_DHR12R2_ADDRESS 0x40007414\r
-\r
-DAC_InitTypeDef DAC_InitStructure;\r
-\r
-/* 32 sample sine wave which at Fs=16kHz will be 500Hz. Note samples\r
- are unsigned */\r
-\r
-const uint16_t aSine12bit[32] = {\r
- 2047, 2447, 2831, 3185, 3498, 3750, 3939, 4056, 4095, 4056,\r
- 3939, 3750, 3495, 3185, 2831, 2447, 2047, 1647, 1263, 909, \r
- 599, 344, 155, 38, 0, 38, 155, 344, 599, 909, 1263, 1647};\r
-\r
-static void TIM6_Config(void);\r
-static void DAC_Ch2_SineWaveConfig(void);\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
-\r
-int main(void)\r
-{\r
- /*!< At this stage the microcontroller clock setting is already configured, \r
- this is done through SystemInit() function which is called from startup\r
- files (startup_stm32f40xx.s/startup_stm32f427x.s) before to branch to \r
- application main. \r
- To reconfigure the default setting of SystemInit() function, refer to\r
- system_stm32f4xx.c file\r
- */ \r
-\r
- /* Preconfiguration before using DAC----------------------------------------*/\r
- GPIO_InitTypeDef GPIO_InitStructure;\r
-\r
- /* DMA1 clock enable */\r
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);\r
- /* GPIOA clock enable (to be used with DAC) */\r
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); \r
- /* DAC Periph clock enable */\r
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);\r
-\r
- /* DAC channel 1 & 2 (DAC_OUT1 = PA.4)(DAC_OUT2 = PA.5) configuration */\r
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;\r
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;\r
- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
- GPIO_Init(GPIOA, &GPIO_InitStructure);\r
-\r
- /* TIM6 Configuration ------------------------------------------------------*/\r
-\r
- TIM6_Config(); \r
- \r
- DAC_Ch2_SineWaveConfig();\r
-\r
- while (1);\r
-}\r
+#define SINE_SAMPLES 32\r
\r
-/** \r
- * @brief TIM6 Configuration\r
- * @note TIM6 configuration is based on APB1 frequency\r
- * @note TIM6 Update event occurs each TIM6CLK/256 \r
- * @param None\r
- * @retval None\r
- */\r
-static void TIM6_Config(void)\r
-{\r
- TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
- /* TIM6 Periph clock enable */\r
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);\r
- \r
- /* --------------------------------------------------------\r
- \r
- TIM3 input clock (TIM6CLK) is set to 2 * APB1 clock (PCLK1), since\r
- APB1 prescaler is different from 1 (see system_stm32f4xx.c and Fig\r
- 13 clock tree figure in DM0031020.pdf).\r
-\r
- Sample rate Fs = 2*PCLK1/TIM_ClockDivision \r
- = (HCLK/2)/TIM_ClockDivision\r
- \r
- ----------------------------------------------------------- */\r
-\r
- /* Time base configuration */\r
- TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); \r
- TIM_TimeBaseStructure.TIM_Period = 5250; \r
- TIM_TimeBaseStructure.TIM_Prescaler = 0; \r
- TIM_TimeBaseStructure.TIM_ClockDivision = 0; \r
- TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; \r
- TIM_TimeBaseInit(TIM6, &TIM_TimeBaseStructure);\r
-\r
- /* TIM6 TRGO selection */\r
- TIM_SelectOutputTrigger(TIM6, TIM_TRGOSource_Update);\r
- \r
- /* TIM6 enable counter */\r
- TIM_Cmd(TIM6, ENABLE);\r
-}\r
\r
-/**\r
- * @brief DAC Channel2 SineWave Configuration\r
- * @param None\r
- * @retval None\r
- */\r
-static void DAC_Ch2_SineWaveConfig(void)\r
-{\r
- DMA_InitTypeDef DMA_InitStructure;\r
- NVIC_InitTypeDef NVIC_InitStructure;\r
- \r
- /* DAC channel2 Configuration */\r
- DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;\r
- DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;\r
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
- DAC_Init(DAC_Channel_2, &DAC_InitStructure);\r
-\r
- /* DMA1_Stream6 channel7 configuration **************************************/\r
- DMA_DeInit(DMA1_Stream6);\r
- DMA_InitStructure.DMA_Channel = DMA_Channel_7; \r
- DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12R2_ADDRESS;\r
- DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&aSine12bit;\r
- DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;\r
- DMA_InitStructure.DMA_BufferSize = 32;\r
- DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
- DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;\r
- DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;\r
- DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;\r
- DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;\r
- DMA_InitStructure.DMA_Priority = DMA_Priority_High;\r
- DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; \r
- DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;\r
- DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;\r
- DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;\r
- DMA_Init(DMA1_Stream6, &DMA_InitStructure);\r
-\r
- /* Enable DMA Half 7 Complete interrupts */\r
- DMA_ITConfig(DMA1_Stream6, DMA_IT_TC | DMA_IT_HT, ENABLE);\r
-\r
- /* Enable the DMA Stream IRQ Channel */\r
-\r
- NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream6_IRQn;\r
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;\r
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
- NVIC_Init(&NVIC_InitStructure); \r
-\r
- /* Enable DMA1_Stream6 */\r
- DMA_Cmd(DMA1_Stream6, ENABLE);\r
-\r
- /* Enable DAC Channel2 */\r
- DAC_Cmd(DAC_Channel_2, ENABLE);\r
-\r
- /* Enable DMA for DAC Channel2 */\r
- DAC_DMACmd(DAC_Channel_2, ENABLE);\r
+/* 32 sample sine wave which at Fs=16kHz will be 500Hz. Not sampels\r
+ are 16 bit 2's complement, the DAC driver convertsto 12 bit\r
+ unsigned. */\r
+\r
+const short aSine[] = {\r
+ -16, 6384, 12528, 18192, 23200, 27232, 30256, 32128, 32752, 32128,\r
+ 30256, 27232, 23152, 18192, 12528, 6384, -16, -6416, -12560, -18224,\r
+ -23184, -27264, -30288, -32160, -32768, -32160, -30288, -27264, -23184, -18224,\r
+ -12560, -6416\r
+};\r
+\r
+int main(void) {\r
+\r
+ dac_open();\r
+\r
+ while (1) {\r
+\r
+ /* keep DAC FIFO topped up */\r
+\r
+ dac_write((short*)aSine, SINE_SAMPLES);\r
+ }\r
+ \r
}\r
\r
--- /dev/null
+/*---------------------------------------------------------------------------*\\r
+\r
+ FILE........: stm32f4_dac.c\r
+ AUTHOR......: David Rowe\r
+ DATE CREATED: 1 June 2013\r
+\r
+ DAC driver module for STM32F4.\r
+\r
+\*---------------------------------------------------------------------------*/\r
+\r
+/*\r
+ Copyright (C) 2013 David Rowe\r
+\r
+ All rights reserved.\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU Lesser General Public License version 2.1, as\r
+ published by the Free Software Foundation. This program is\r
+ distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\r
+ License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public License\r
+ along with this program; if not, see <http://www.gnu.org/licenses/>.\r
+*/\r
+\r
+#include <assert.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "stm32f4xx.h"\r
+#include "codec2_fifo.h"\r
+#include "stm32f4_dac.h"\r
+\r
+#define DAC_DHR12R2_ADDRESS 0x40007414\r
+#define DAC_DHR12L2_ADDRESS 0x40007418\r
+\r
+#define DAC_BUF_SZ 320\r
+#define FIFO_SZ 2000\r
+#define DAC_MAX 4096\r
+\r
+DAC_InitTypeDef DAC_InitStructure;\r
+struct FIFO *DMA1_Stream6_fifo;\r
+\r
+unsigned short dac_buf[DAC_BUF_SZ];\r
+\r
+static void TIM6_Config(void);\r
+static void DAC_Ch2_Config(void);\r
+\r
+void dac_open(void) {\r
+\r
+ memset(dac_buf, 32768, sizeof(short)*DAC_BUF_SZ);\r
+\r
+ /* Create fifo */\r
+\r
+ DMA1_Stream6_fifo = fifo_create(FIFO_SZ);\r
+ assert(DMA1_Stream6_fifo != NULL);\r
+\r
+ /*!< At this stage the microcontroller clock setting is already configured, \r
+ this is done through SystemInit() function which is called from startup\r
+ files (startup_stm32f40xx.s/startup_stm32f427x.s) before to branch to \r
+ application main. \r
+ To reconfigure the default setting of SystemInit() function, refer to\r
+ system_stm32f4xx.c file\r
+ */ \r
+\r
+ /* Preconfiguration before using DAC----------------------------------------*/\r
+\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* DMA1 clock enable */\r
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);\r
+ /* GPIOA clock enable (to be used with DAC) */\r
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); \r
+ /* DAC Periph clock enable */\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);\r
+\r
+ /* DAC channel 1 & 2 (DAC_OUT1 = PA.4)(DAC_OUT2 = PA.5) configuration */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_Init(GPIOA, &GPIO_InitStructure);\r
+\r
+ /* TIM6 Configuration ------------------------------------------------------*/\r
+\r
+ TIM6_Config(); \r
+ DAC_Ch2_Config();\r
+ \r
+}\r
+\r
+/* Accepts signed 16 bit samples */\r
+\r
+int dac_write(short buf[], int n) { \r
+ return fifo_write(DMA1_Stream6_fifo, buf, n);\r
+}\r
+\r
+/** \r
+ * @brief TIM6 Configuration\r
+ * @note TIM6 configuration is based on APB1 frequency\r
+ * @note TIM6 Update event occurs each TIM6CLK/256 \r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void TIM6_Config(void)\r
+{\r
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
+ /* TIM6 Periph clock enable */\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);\r
+ \r
+ /* --------------------------------------------------------\r
+ \r
+ TIM3 input clock (TIM6CLK) is set to 2 * APB1 clock (PCLK1), since\r
+ APB1 prescaler is different from 1 (see system_stm32f4xx.c and Fig\r
+ 13 clock tree figure in DM0031020.pdf).\r
+\r
+ Sample rate Fs = 2*PCLK1/TIM_ClockDivision \r
+ = (HCLK/2)/TIM_ClockDivision\r
+ \r
+ ----------------------------------------------------------- */\r
+\r
+ /* Time base configuration */\r
+ TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); \r
+ TIM_TimeBaseStructure.TIM_Period = 5250; \r
+ TIM_TimeBaseStructure.TIM_Prescaler = 0; \r
+ TIM_TimeBaseStructure.TIM_ClockDivision = 0; \r
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; \r
+ TIM_TimeBaseInit(TIM6, &TIM_TimeBaseStructure);\r
+\r
+ /* TIM6 TRGO selection */\r
+ TIM_SelectOutputTrigger(TIM6, TIM_TRGOSource_Update);\r
+ \r
+ /* TIM6 enable counter */\r
+ TIM_Cmd(TIM6, ENABLE);\r
+}\r
+\r
+/**\r
+ * @brief DAC Channel2 SineWave Configuration\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void DAC_Ch2_Config(void)\r
+{\r
+ DMA_InitTypeDef DMA_InitStructure;\r
+ NVIC_InitTypeDef NVIC_InitStructure;\r
+ \r
+ /* DAC channel2 Configuration */\r
+ DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;\r
+ DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;\r
+ DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+ DAC_Init(DAC_Channel_2, &DAC_InitStructure);\r
+\r
+ /* DMA1_Stream6 channel7 configuration **************************************/\r
+ DMA_DeInit(DMA1_Stream6);\r
+ DMA_InitStructure.DMA_Channel = DMA_Channel_7; \r
+ DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12L2_ADDRESS;\r
+ DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dac_buf;\r
+ DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;\r
+ DMA_InitStructure.DMA_BufferSize = DAC_BUF_SZ;\r
+ DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+ DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;\r
+ DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;\r
+ DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;\r
+ DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;\r
+ DMA_InitStructure.DMA_Priority = DMA_Priority_High;\r
+ DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; \r
+ DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;\r
+ DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;\r
+ DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;\r
+ DMA_Init(DMA1_Stream6, &DMA_InitStructure);\r
+\r
+ /* Enable DMA Half 7 Complete interrupts */\r
+ DMA_ITConfig(DMA1_Stream6, DMA_IT_TC | DMA_IT_HT, ENABLE);\r
+\r
+ /* Enable the DMA Stream IRQ Channel */\r
+\r
+ NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream6_IRQn;\r
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;\r
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+ NVIC_Init(&NVIC_InitStructure); \r
+\r
+ /* Enable DMA1_Stream6 */\r
+ DMA_Cmd(DMA1_Stream6, ENABLE);\r
+\r
+ /* Enable DAC Channel2 */\r
+ DAC_Cmd(DAC_Channel_2, ENABLE);\r
+\r
+ /* Enable DMA for DAC Channel2 */\r
+ DAC_DMACmd(DAC_Channel_2, ENABLE);\r
+}\r
+\r
+/******************************************************************************/\r
+/* STM32F4xx Peripherals Interrupt Handlers */\r
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r
+/* available peripheral interrupt handler's name please refer to the startup */\r
+/* file (startup_stm32f40xx.s/startup_stm32f427x.s). */\r
+/******************************************************************************/\r
+\r
+/*\r
+ This function handles DMA Stream interrupt request.\r
+*/\r
+\r
+void DMA1_Stream6_IRQHandler(void) {\r
+ int i, sam;\r
+ short signed_buf[DAC_BUF_SZ/2];\r
+\r
+ /* Transfer half empty interrupt */\r
+\r
+ if(DMA_GetITStatus(DMA1_Stream6, DMA_IT_HTIF6) != RESET) {\r
+ /* fill first half from fifo */\r
+\r
+ if (fifo_read(DMA1_Stream6_fifo, signed_buf, DAC_BUF_SZ/2) == -1)\r
+ memset(signed_buf, 0, sizeof(short)*DAC_BUF_SZ/2);\r
+\r
+ /* convert to unsigned */\r
+\r
+ for(i=0; i<DAC_BUF_SZ/2; i++) {\r
+ sam = (int)signed_buf[i] + 32768;\r
+ dac_buf[i] = (unsigned short)(sam);\r
+ }\r
+\r
+ /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
+\r
+ DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_HTIF6); \r
+ }\r
+\r
+ /* Transfer complete interrupt */\r
+\r
+ if(DMA_GetITStatus(DMA1_Stream6, DMA_IT_TCIF6) != RESET) {\r
+ /* fill second half from fifo */\r
+\r
+ if (fifo_read(DMA1_Stream6_fifo, signed_buf, DAC_BUF_SZ/2) == -1)\r
+ memset(signed_buf, 0, sizeof(short)*DAC_BUF_SZ/2);\r
+\r
+ /* convert to unsigned */\r
+\r
+ for(i=0; i<DAC_BUF_SZ/2; i++) {\r
+ sam = (int)signed_buf[i] + 32768;\r
+ dac_buf[i+DAC_BUF_SZ/2] = (unsigned short)(sam);\r
+ }\r
+\r
+ /* Clear DMA Stream Transfer Complete interrupt pending bit */\r
+\r
+ DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_TCIF6); \r
+ }\r
+}\r
projects / freetel-svn-tracking.git / commitdiff