dac.vbias_buf(100e-3)
# zero others
+# part A already POR's to 0 but...
for i in range(5, 8):
dac.setv(i, 0.0)
adc.convst_spi(1)
# dac.vina --> adc.ch4
+# J604 -- J210
adc.mux(4)
#ch4 setup
n = []
r = []
- for i in range(2**10):
- x = 2**6 * i
+ nbits = 16
+ for i in range(2**nbits):
+ x = 2**(16-nbits) * i
dac.set(0, x)
adc.read() #sham to trigger conversion
- sleep(200e-6) #ensure 160us conversion time delay
+ sleep(160e-6) #ensure 160us conversion time delay
n.append(x)
v = adc.read()
r.append(v)
- print x, v
+ if i % 256 == 0:
+ print x, v
- if 0:
+ if 1:
figure()
plot(n, r)
xlabel('DAC code')
class DAC8568(object):
CTL_WIDTH = 32
DAC_WIDTH = 16
- POR_VALUE = 2**(DAC_WIDTH - 1)
+ #POR_VALUE = 2**(DAC_WIDTH - 1)
+ POR_VALUE = 0
ALL_CHANNELS = 0xf
class DAC_atoi(DAC8568):
"""Specific configuration and calibration for devboard DAC."""
VREF = 2.5
- GAIN = 2.0 #part options C/D
- #POR_VALUE = 0 #part C
- POR_VALUE = DAC8568.DAC_WIDTH / 2 #part D
+ GAIN = 1.0 #part options A/B
+ #GAIN = 2.0 #part options C/D
+ POR_VALUE = 0 #part A/C
+ #POR_VALUE = DAC8568.DAC_WIDTH / 2 #part B/D
#zero-code output voltages
VOS = ( 0.0,
0.0,
0.0,
- 5e-3,
+ 0.0,
0.0,
0.0,
0.0,