updated power budget and task list

git-svn-id: https://svn.code.sf.net/p/freetel/code@2624 01035d8c-6547-0410-b346-abe4f91aad63

diff --git a/sm2000/doc/sm202 Task List.txt b/sm2000/doc/sm202 Task List.txt
index 9fe3258fec1ea9b4e7d63723ef34849154a743c1..3de0a771bf09e40f56def3c1f3474d7d9a12e1e6 100644 (file)
--- a/sm2000/doc/sm202 Task List.txt
+++ b/sm2000/doc/sm202 Task List.txt
@@ -230,14 +230,15 @@ Task List
     [ ] Dual freq TDMA\r
         + tx and rx?  We need a way to tx on two different freqs\r
         + use same clock for tx and rx?\r
-    [ ] 2ND LO dist and swicthing\r
+    [X] 2ND LO dist and swicthing\r
         + 150pF to NE602?\r
         + attenuator?\r
         + selecting LOs?\r
     [ ] Spreadsheet with Z matches\r
+    [ ] check power consumption on each rail matches regulator limits\r
 \r
 [ ] Sch Entry\r
-    [ ] linear reg option for vadc ADC and vref\r
+    [X] linear reg option for vadc ADC and vref\r
         + jumper select to test\r
     [ ] put extra 0805 or 1206 components in parallel for Z matching and DNL\r
         + e.g. on collectors and emitters of RF amps\r
@@ -250,16 +251,16 @@ Task List
         [ ] location of shields if rqd\r
         [ ] how to adjust/if adjustment rqd\r
             + e.g. adjust filter by variation in coild spacing against filter spec\r
-    [ ] 4 by 0.1 inch pin headers in a square pattern to disconnect building blocks    \r
+    [X] 4 by 0.1 inch pin headers in a square pattern to disconnect building blocks    \r
     [X] select Si570 with a jumper\r
     [ ] review of foot prints for discretes\r
         + ease of debug, e.g. if we need to add a LC filter\r
         + power handling\r
-    [ ] check package of each L\r
+    [X] check package of each L\r
         + make sure enough room for hand wound air core versions\r
-    [ ] specify locations of 4 pin 50 ohm breaks\r
+    [X] specify locations of 4 pin 50 ohm breaks\r
         + 0805 0 ohm, or break for isolation and testing\r
-    [ ] 10uF tant to PA\r
+    [X] PS filter for PA\r
     [X] research TXCO for si5351 clock input\r
         + perhaps include as option\r
         + does it have to be 25MHz?\r
@@ -267,10 +268,16 @@ Task List
     [ ] how to connect SCA/SCL on clock chips to uC?\r
         + is there a separate enable?\r
     [ ] LEDs for control signals/rails\r
-    [ ] Add a Av=2 op-amp to take 3v3 DAC max from uC to 5V\r
+    [X] Add a Av=2 op-amp to take 3v3 DAC max from uC to 5V\r
         max for Vgg driving PA final Q14.  Will need to be powered by 5V rail.\r
         This is a preacuation in case we need > 3V for some FETs\r
-\r
+    [ ] Vgg PWM filtering\r
+        + we use PWM to genrate a bias for VGG\r
+        + this needs to be filtered so we don't modulate the PA output\r
+        + but we also need a faily fast respomse time, e.g. 1ms from\r
+          0V to Vgg set point to modulate PA power for TDMA.\r
+    [ ] consider shared clock for Si5351 and uC\r
+   \r
 [ ] Rev A PCB Layout\r
     [ ] footprints for all devices\r
     [ ] will air core inductors be thru hole parts?\r

diff --git a/sm2000/doc/sm205_power_budget.xls b/sm2000/doc/sm205_power_budget.xls
index e9d6bb89d957ac53f3eba88e3f75b6b8ae6a5a3d..92bc4628a01a10cc32a78192c37eece6c4280ddd 100644 (file)
Binary files a/sm2000/doc/sm205_power_budget.xls and b/sm2000/doc/sm205_power_budget.xls differ