From: Dan White Date: Wed, 25 Jan 2012 19:45:15 +0000 (-0600) Subject: WIP pinout X-Git-Tag: calibrations~335 X-Git-Url: http://git.whiteaudio.com/gitweb/?a=commitdiff_plain;h=102674e6aa72bf265b325aed59b3a2a18d5f6533;p=430.git WIP pinout --- diff --git a/test-pcb/pinout-notes.otl b/test-pcb/pinout-notes.otl index 8aa2649..819bab7 100644 --- a/test-pcb/pinout-notes.otl +++ b/test-pcb/pinout-notes.otl @@ -45,8 +45,12 @@ Power [X] 100% AD5242 - dual 100k pot (LDO) : DigiPot1 [X] 2.2 Vmin + [X] 100% M25PExx - serial flash + : Flash0 + [X] 2.7 Vmin [X] 100% By-PS-Domain - [_] 0% DCDC - supplies all others + [X] 100% DCDC - supplies all others + : do not use [X] 100% LDO0 - Digital : ADP323 triple adj LDO with EN : Needs separate >= 2.5 Vbias @@ -67,7 +71,7 @@ Power [X] cc430 DVCC [X] cc430 AVcc_RF [X] cc430 AVcc - [X] AVdd_dev - peripheral analog 2.7 V + [X] AVdd_dev - peripheral analog, flash 2.7 V : full dev board - fixed at 2.7 V : ADC0 and DigiPotX may be 2.2 V for small board [X] ADC0 VD @@ -75,6 +79,7 @@ Power [X] DAC0 AVdd [X] DigiPot0 Vdd [X] DigiPot1 Vdd + [X] Flash0 @@ -187,10 +192,10 @@ Connections [_] mux1_outB - Arb mux/buffer output [_] send to ADC - [_] 0% cc430f5137 + [_] 16% cc430f5137 : on board - [_] 0% Pins - RF + [_] 16% Pins + [_] 0% RF RFIO [_] 29- RF_P [_] 30- RF_N @@ -202,7 +207,7 @@ Connections [_] 12- P1.1/RFGDO2 [_] 13- P1.0/RFGDO0 [_] 15- P3.6/RFGDO1 - Comm + [_] 0% Comm : UCA0 supports SPI, UART : UCB0 supports SPI, I2C [_] 4 - P1.7/UCA0CLK/UCB0STE @@ -211,27 +216,30 @@ Connections [_] 9 - P1.4/UCB0CLK/UCA0STE [_] 10- P1.3/UCB0MOSI/UCB0SDA [_] 11- P1.2/UCB0MISO/UCB0SCL - Sys / JTAG / SpyBiWire + [_] 0% Sys / JTAG / SpyBiWire [_] 35- PJ.0/TDO [_] 36- PJ.1/TDI/TCLK [_] 37- PJ.2/TMS [_] 38- PJ.3/TCK [_] 39- TEST/SBWTCK [_] 40- \_RST\_/NMI/SBWTDIO - Power - [_] 7 - VCORE - [_] 8 - DVCC - [_] 27- AVCC_RF - [_] 28- AVCC_RF - [_] 31- AVCC_RF - [_] 32- AVCC_RF - [_] 22- DVCC - [_] 34- GUARD - [_] 41- DVCC - [_] 42- AVSS - [_] 45- AVCC - [_] 49- VSS_EP - ADC12 / Comp / Ref + [_] 43- P5.1/XOUT + [_] 44- P5.0/Xi + [X] 100% Power + [X] 7 - VCORE + : filter cap only + [X] 8 - DVCC + [X] 27- AVCC_RF + [X] 28- AVCC_RF + [X] 31- AVCC_RF + [X] 32- AVCC_RF + [X] 22- DVCC + [X] 34- GUARD + [X] 41- DVCC + [X] 42- AVSS + [X] 45- AVCC + [X] 49- VSS_EP + [_] 0% ADC12 / Comp / Ref : x - arb_out0 ?? : x - arb_out1 ?? : - IVdd_ns430 @@ -246,9 +254,7 @@ Connections [_] 1 - P2.2/TA1CCR1A/CB2/A2 [_] 2 - P2.1/TA1CCR0A/CB1/A1 [_] 3 - P2.0/CBOUT1/TA1CLK/CB0/A0 - Timing / GP - [_] 43- P5.1/XOUT - [_] 44- P5.0/Xi + [_] 0% Timing / GP [_] 14- P3.7/SMCLK [_] 24- P2.6/ACLK [_] 16- P3.5/TA0CCR4A @@ -258,7 +264,7 @@ Connections [_] 20- P3.1/TA0CCR0A [_] 21- P3.0/CBOUT0/TA0CLK [_] 23- P2.7/ADC12CLK/DMAE0 - [_] 4% ADC0 - shared SPI bus + [_] 47% ADC0 - shared SPI bus : ADS8201 (sampled from TI) : QFN-24 : needs Vref @@ -266,41 +272,41 @@ Connections [_] 0% Control [_] SPI1 on ns430 [_] USCI_A0 or USCI_B0 on cc430 - [_] 0% Input Signals - [_] 0 - biasR - to infer bias current + [X] 100% Input Signals + [X] 0 - biasR - to infer bias current : diff with 5 for Vrdac0, or SE for PTAT n*Vt*ln(k) : buffered by max9912 - [_] 1 - 1k biasR Vx + [X] 1 - 1k biasR Vx : buffered by max9912 - [_] 2 - buf_biasR - to infer bias current + [X] 2 - buf_biasR - to infer bias current : diff with 7 for Vrdac1, or SE for PTAT n*Vt*ln(k) : buffered by max9912 - [_] 3 - 1k buf_biasR Vx + [X] 3 - 1k buf_biasR Vx : buffered by max9912 - [_] 4 - mux0_outA - [_] 5 - mux0_outB - [_] 6 - mux1_outA + [X] 4 - mux0_outA + [X] 5 - mux0_outB + [X] 6 - mux1_outA : or by pcb switch arb_out0 - hardwired to arb0 - [_] 7 - mux1_outB + [X] 7 - mux1_outB : or by pcb switch arb_out1 - hardwired to arb0 - [_] 14% Pins - [_] IN[7:0] + [_] 42% Pins + [X] IN[7:0] [_] /RST - hardware reset [_] BUSY/INT - indication of activity [_] SCLK, SDI, SDO, /CS - [_] DGND - interface gnd + [X] DGND - interface gnd [_] /CONVST [X] VD - interface supply [X] VA - analog supply [_] REF - external reference - [_] REFGND - reference gnd - [_] AGND - analog gnd + [X] REFGND - reference gnd + [X] AGND - analog gnd [_] ADCIN - ADC input [_] PGAOUT - connected (opt filtered) to ADCIN : PCB footprints for RC filter or short-to-ADCIN [_] PGAREF - set to Vanalog/2 for signed codes : switchable between gnd and Vref/2 - [_] 2% DAC0 - shared SPI bus + [_] 4% DAC0 - shared SPI bus : DAC8568 (sampled from TI) : TSSOP-16 : 8ch 16bit 2.7 Vmin @@ -317,8 +323,9 @@ Connections [_] x - [_] x - [_] x - - [_] 6% Pins + [_] 12% Pins [_] 1 - /LDAC - load DACs + : tie to extra pin for flexibility [_] 2 - /SYNC - SPI /CS - frame sync input data [X] 3 - AVDD [_] 4 - VoutA @@ -331,43 +338,43 @@ Connections [_] 11- VoutF [_] 12- VoutD [_] 13- VoutB - [_] 14- GND + [X] 14- GND [_] 15- DIN - SPI MOSI [_] 16- SCLK - SPI clock - [_] 0% DigiPot0 - shared I2C bus + [_] 65% DigiPot0 - shared I2C bus : AD5242 (sampled from ADI) : 1M 256tap I2C pot 2.7 Vmin : TSSOP-16 [_] 0% Control [_] I2C on ns430 [_] USCI_B0 on cc430 - [_] 0% Pot1 - [_] A1 - open, test point - [_] W1 - biasR pin, ADC in - [_] B1 - 1k top, ADC in + [X] 100% Pot1 + [X] A1 - open, test point + [X] W1 - biasR pin, ADC in + [X] B1 - 1k top, ADC in : 1k bottom to AGND - [_] 0% Pot2 - [_] A2 - open, test point - [_] W2 - buf_biasR pin, ADC in - [_] B2 - 1k top, ADC in + [X] 100% Pot2 + [X] A2 - open, test point + [X] W2 - buf_biasR pin, ADC in + [X] B2 - 1k top, ADC in : 1k bottom to AGND - [_] 0% Pins + [_] 62% Pins [_] 1 - O1 - logic out1 - [_] 2 - A1 - pot1 top - [_] 3 - W1 - pot1 wiper - [_] 4 - B1 - pot1 bottom - [_] 5 - VDD - 2.2-5.5V - [_] 6 - /SHDN - async short W-B, tie to VDD + [X] 2 - A1 - pot1 top + [X] 3 - W1 - pot1 wiper + [X] 4 - B1 - pot1 bottom + [X] 5 - VDD - 2.2-5.5V + [X] 6 - /SHDN - async short W-B, tie to VDD [_] 7 - SCL - I2C clock [_] 8 - SDA - I2C data [_] 9 - AD0 - I2C address0 [_] 10- AD1 - I2C address1 - [_] 11- DGND - logic common - [_] 12- VSS - lowest Vpot - (-2.7-0V) + [X] 11- DGND - logic common + [X] 12- VSS - lowest Vpot - (-2.7-0V) [_] 13- O2 - logic out2 - [_] 14- B2 - pot2 bottom - [_] 15- W2 - pot2 wiper - [_] 16- A2 - pot2 top + [X] 14- B2 - pot2 bottom + [X] 15- W2 - pot2 wiper + [X] 16- A2 - pot2 top [_] 0% DigiPot1 - shared I2C bus : AD5242 (sampled from ADI) : 100k 256tap I2C pot 2.7 Vmin @@ -400,5 +407,18 @@ Connections [_] 14- B2 - pot2 bottom [_] 15- W2 - pot2 wiper [_] 16- A2 - pot2 top + [_] 18% M25PExx flash + [_] 0% Control + [_] SPI0 on ns430 + [_] 37% Pins + [_] 1 - /S - chip select + [_] 2 - Q - MISO + [X] 3 - /W - write protect + : tie high + [X] 4 - Vss + [_] 5 - D - MOSI + [_] 6 - C - SCLK + [_] 7 - /Reset + [X] 8 - Vcc (2.7 Vmin)