From: drowe67 <drowe67@01035d8c-6547-0410-b346-abe4f91aad63>
Date: Fri, 11 Jul 2014 04:41:28 +0000 (+0000)
Subject: basic UT working on SM1000
X-Git-Url: http://git.whiteaudio.com/gitweb/?a=commitdiff_plain;h=790f2d44fa7806b65d4be0e6bd4cf8c10b3dbcfb;p=freetel-svn-tracking.git

basic UT working on SM1000

git-svn-id: https://svn.code.sf.net/p/freetel/code@1754 01035d8c-6547-0410-b346-abe4f91aad63
---

diff --git a/codec2-dev/stm32/Makefile b/codec2-dev/stm32/Makefile
index dbda50e0..917e1ae2 100644
--- a/codec2-dev/stm32/Makefile
+++ b/codec2-dev/stm32/Makefile
@@ -14,7 +14,7 @@ SIZE=$(BINPATH)/arm-none-eabi-size
 
 ###################################################
 
-CFLAGS  = -std=gnu99 -O2 -g -Wall -Tstm32_flash.ld -DSTM32F4XX -DCORTEX_M4
+CFLAGS  = -std=gnu99 -O0 -g -Wall -Tstm32_flash.ld -DSTM32F4XX -DCORTEX_M4
 CFLAGS += -mlittle-endian -mthumb -mthumb-interwork -nostartfiles -mcpu=cortex-m4
 
 ifeq ($(FLOAT_TYPE), hard)
diff --git a/codec2-dev/stm32/src/stm32f4_dac.c b/codec2-dev/stm32/src/stm32f4_dac.c
index 8ef8107f..caa43ce3 100644
--- a/codec2-dev/stm32/src/stm32f4_dac.c
+++ b/codec2-dev/stm32/src/stm32f4_dac.c
@@ -36,7 +36,7 @@
 #define DAC_DHR12L2_ADDRESS    0x40007418
 
 #define DAC_BUF_SZ   320
-#define FIFO_SZ      1000
+#define FIFO_SZ      4*DAC_BUF_SZ
 #define DAC_MAX      4096
 
 DAC_InitTypeDef  DAC_InitStructure;
diff --git a/codec2-dev/stm32/src/stm32f4_pwm.c b/codec2-dev/stm32/src/stm32f4_pwm.c
index 776baf54..2d467e00 100644
--- a/codec2-dev/stm32/src/stm32f4_pwm.c
+++ b/codec2-dev/stm32/src/stm32f4_pwm.c
@@ -98,6 +98,7 @@ static void TIM_Config(void)
   GPIO_Init(GPIOB, &GPIO_InitStructure);
   GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_TIM1);
 
+#ifdef DR_OFF
   /* DMA clock enable */
   RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 , ENABLE);
 
@@ -119,6 +120,7 @@ static void TIM_Config(void)
   DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
 
   DMA_Init(DMA2_Stream6, &DMA_InitStructure);
+#endif
 }
 
 void Timer1Config() {
@@ -158,7 +160,7 @@ void Timer1Config() {
 
 #ifdef TMP
     uhTimerPeriod = (SystemCoreClock / FS ) - 1;
-    gdb_stdio_printf("uhTimerPeriod = %d\n", uhTimerPeriod);
+    //gdb_stdio_printf("uhTimerPeriod = %d\n", uhTimerPeriod);
 
     /* Compute CCR1 values to generate a duty cycle at 50% */
 
@@ -166,24 +168,11 @@ void Timer1Config() {
         aSRC_Buffer[i] = uhTimerPeriod *((int)aSine[i] + 32768)/(32768*2);
     }
 #else
-    uhTimerPeriod = (SystemCoreClock / 42000000 ) - 1;
-    gdb_stdio_printf("uhTimerPeriod = %d\n", uhTimerPeriod);
-
-    /* Compute CCR1 values to generate a duty cycle at 50% */
-
-    aSRC_Buffer[0] = 2;
-#endif
-
-#ifdef OLD
-  /* Compute CCR1 value to generate a duty cycle at 50% */
-  aSRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (uhTimerPeriod - 1)) / 10);
-  /* Compute CCR1 value to generate a duty cycle at 37.5% */
-  aSRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (uhTimerPeriod - 1)) / 1000);
-  /* Compute CCR1 value to generate a duty cycle at 25% */
-  aSRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (uhTimerPeriod - 1)) / 100);
+    uhTimerPeriod = (SystemCoreClock / 28000000) - 1;
+    aSRC_Buffer[0] =   uhTimerPeriod/2 + 1;
+    
 #endif
 
-    /* TIM1 Peripheral Configuration -------------------------------------------*/
     /* TIM1 clock enable */
 
     RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
@@ -199,6 +188,9 @@ void Timer1Config() {
 
     TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
 
+
+    #define TMP2
+#ifdef TMP2
     /* Channel 3 Configuration in PWM mode */
 
     TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
@@ -214,7 +206,25 @@ void Timer1Config() {
 
     /* Enable preload feature */
     TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);
-  
+#else
+    /* Channel 3 Configuration in PWM mode */
+
+    TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
+    TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+    //TIM_OCInitStructure.TIM_Pulse = aSRC_Buffer[0];
+
+    //TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
+    //TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
+
+    //TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+    //TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
+    //TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
+
+    TIM_OC3Init(TIM1, &TIM_OCInitStructure);
+
+    //TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);
+#endif
+ 
     /* TIM1 counter enable */
     TIM_Cmd(TIM1, ENABLE);
   
diff --git a/codec2-dev/stm32/src/system_stm32f4xx.c b/codec2-dev/stm32/src/system_stm32f4xx.c
index e1aae444..86953137 100644
--- a/codec2-dev/stm32/src/system_stm32f4xx.c
+++ b/codec2-dev/stm32/src/system_stm32f4xx.c
@@ -153,8 +153,8 @@
 
 /************************* PLL Parameters *************************************/
 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-#define PLL_M      7
-#define PLL_N      342
+#define PLL_M      8
+#define PLL_N      336
 
 /* SYSCLK = PLL_VCO / PLL_P */
 #define PLL_P      2