From: Dan White Date: Mon, 23 Jan 2012 21:15:25 +0000 (-0600) Subject: Power domain planning X-Git-Tag: calibrations~338 X-Git-Url: http://git.whiteaudio.com/gitweb/?a=commitdiff_plain;h=797fd2a81ac17eb584a8ebeeca0a736c68219a6a;p=430.git Power domain planning --- diff --git a/test-pcb/pinout-notes.otl b/test-pcb/pinout-notes.otl index ea7671a..80ef6cd 100644 --- a/test-pcb/pinout-notes.otl +++ b/test-pcb/pinout-notes.otl @@ -64,32 +64,77 @@ Notes After boot, r9 holds RAMER count Power - [_] 0% By-IC - [_] 0% wb430 - [_] 0% AtoI - [_] AVDD Analog 2.5V + [_] 91% By-IC + [_] 50% wb430 + [_] 50% AtoI + [X] AVDD Analog 2.5V [_] AVSS Analog gnd - [_] VDD_atoi digital core 1.2V + [X] VDD_atoi digital core 1.2V [_] VSS_atoi digital core gnd - [_] 0% NS430 - [_] DVDD PadIO 2.5V - [_] DVDD PadIO gnd - [_] DVDD OSCIO 2.5V - [_] DVSS OSCIO gnd - [_] VDD 430 core 1.2V - [_] VSS 430 core gnd - [_] VDD osc core 1.2V - [_] VSS osc core gnd - [_] 0% cc430 + [_] 50% NS430 + [X] DVDD_PadIO 2.5V + [_] DVDD_PadIO gnd + [X] DVDD_OSCIO 2.5V + [_] DVSS_OSCIO gnd + [X] VDD_430 core 1.2V + [_] VSS_430 core gnd + [X] VDD_osc core 1.2V + [_] VSS_osc core gnd + [X] 100% cc430 Processor : PMMCOREV modes : 3 - DVcc 2.4 Vmin : 2 - DVcc 2.2 Vmin : 1 - DVcc 2.0 Vmin : 0 - DVcc 1.8 Vmin + [X] DVCC 2.0 Vnom RF section - VCC 2.0Vmin - [_] % By-PS-Domain + [X] AVcc_RF 2.0 Vmin + ADC12 + [X] AVcc 2.2 Vmin + [X] 100% ADS8201 - 8ch 12b-ADC + : ADC0 + [X] 2.2 Vmin + [X] 100% DAC8568 - 8ch 16b-DAC + : DAC0 + [X] 2.7 Vmin + [X] 100% AD5242 - dual 1M pot (biasR) + : DigiPot0 + [X] 2.2 Vmin + [X] 100% AD5242 - dual 100k pot (LDO) + : DigiPot1 + [X] 2.2 Vmin + + [X] 100% By-PS-Domain + [_] 0% DCDC - supplies all others + [X] 100% LDO0 - Digital + : ADP323 triple adj LDO with EN + : Needs separate >= 2.5 Vbias + [X] Vdd_ns430 - core 1.2 V + [X] wb430 VDD_430 + [X] wb430 VDD_osc + [X] DVdd_ns430 - Pad 2.5 V + [X] wb430 DVDD_PadIO + [X] wb430 DVDD_OSCIO + [X] Vdd_dev - cc430 1.8-3.6 V + [X] cc430 DVCC + [X] cc430 AVcc_RF + [X] cc430 AVcc + [X] 100% LDO1 - AtoI, analog + : ADP323 triple adj LDO with EN + : Needs separate >= 2.5 Vbias + [X] Vdd_digi - AtoI digital core 1.2 V + [X] wb430 VDD_atoi + [X] AVdd_atoi - AtoI analog 2.5V + [X] wb430 AVDD Analog + [X] AVdd_dev - peripheral analog 2.7 V + : full dev board - fixed at 2.7 V + : ADC0 and DigiPotX may be 2.2 V for small board + [X] ADC0 VD + [X] ADC0 VA + [X] DAC0 AVdd + [X] DigiPot0 Vdd + [X] DigiPot0 Vdd @@ -100,7 +145,7 @@ Connections : UART0 - bootloader, comms : UART1 - ??? : I2C - DigiPots (biasR, LDO) - [_] % Digital Pins + [_] 0% Digital Pins [_] 94 - GPOut33 / CS1_mux (pad mux) [_] 95 - GPOut32 / CS1_conf (pad mux) [_] 96 - GPOut1 / MULT1 (pad mux) @@ -145,9 +190,10 @@ Connections : to flash [_] 18- PA0 / CS_flash : to flash - [_] 0% ADC0 - shared SPI bus + [_] 4% ADC0 - shared SPI bus : ADS8201 (sampled from TI) : QFN-24 + : needs Vref : 8ch 12bit 2.2/2.7 Vmin [_] 0% Control [_] SPI1 on ns430 @@ -169,15 +215,15 @@ Connections : or by pcb switch arb_out0 - hardwired to arb0 [_] 7 - mux1_outB : or by pcb switch arb_out1 - hardwired to arb0 - [_] 0% Pins + [_] 14% Pins [_] IN[7:0] [_] /RST - hardware reset [_] BUSY/INT - indication of activity [_] SCLK, SDI, SDO, /CS [_] DGND - interface gnd [_] /CONVST - [_] VD - interface supply - [_] VA - analog supply + [X] VD - interface supply + [X] VA - analog supply [_] REF - external reference [_] REFGND - reference gnd [_] AGND - analog gnd @@ -203,11 +249,11 @@ Connections - Ivdd_430 - Ivdd_atoi - Iavdd - [_] 0% DAC0 - shared SPI bus + [_] 2% DAC0 - shared SPI bus : DAC8568 (sampled from TI) : TSSOP-16 : 8ch 16bit 2.7 Vmin - : 2.5 Vref + : 2.5 Vref out [_] 0% Control [_] SPI1 on ns430 [_] USCI_A0 or USCI_B0 on cc430 @@ -220,10 +266,10 @@ Connections [_] x - [_] x - [_] x - - [_] 0% Pins + [_] 6% Pins [_] 1 - /LDAC - load DACs [_] 2 - /SYNC - SPI /CS - frame sync input data - [_] 3 - AVDD + [X] 3 - AVDD [_] 4 - VoutA [_] 5 - VoutC [_] 6 - VoutE @@ -271,4 +317,36 @@ Connections [_] 14- B2 - pot2 bottom [_] 15- W2 - pot2 wiper [_] 16- A2 - pot2 top + [_] 0% DigiPot1 - shared I2C bus + : AD5242 (sampled from ADI) + : 100k 256tap I2C pot 2.7 Vmin + : TSSOP-16 + [_] 0% Control + [_] I2C on ns430 + [_] USCI_B0 on cc430 + [_] 0% Pot1 + [_] A1 - + [_] W1 - + [_] B1 - + [_] 0% Pot2 + [_] A2 - + [_] W2 - + [_] B2 - + [_] 0% Pins + [_] 1 - O1 - logic out1 + [_] 2 - A1 - pot1 top + [_] 3 - W1 - pot1 wiper + [_] 4 - B1 - pot1 bottom + [_] 5 - VDD - 2.2-5.5V + [_] 6 - /SHDN - async short W-B, tie to VDD + [_] 7 - SCL - I2C clock + [_] 8 - SDA - I2C data + [_] 9 - AD0 - I2C address0 + [_] 10- AD1 - I2C address1 + [_] 11- DGND - logic common + [_] 12- VSS - lowest Vpot - (-2.7-0V) + [_] 13- O2 - logic out2 + [_] 14- B2 - pot2 bottom + [_] 15- W2 - pot2 wiper + [_] 16- A2 - pot2 top