From 56df933597f5750e6f7eda580ec54abe0c473495 Mon Sep 17 00:00:00 2001 From: Dan White Date: Sun, 5 May 2013 23:25:54 -0500 Subject: [PATCH] msp4th: flash boot loader make target "bootrom" sets the correct flags and uses a tweaked ldscript for all the right locations and such. normal make targets, e.g. "all", assume you are building the boot rom for testing in RAM space. NOTE: this requires manually setting the reset vector to 0x4000 instead of the location gcc uses. --- ihex2rcf.py | 58 ++++++ msp4th/Makefile | 20 +- msp4th/flashboot.s | 149 +++++++++------ msp4th/ldscript_ns430_bootrom | 340 ++++++++++++++++++++++++++++++++++ msp4th/main.c | 38 ++-- 5 files changed, 525 insertions(+), 80 deletions(-) create mode 100755 ihex2rcf.py create mode 100644 msp4th/ldscript_ns430_bootrom diff --git a/ihex2rcf.py b/ihex2rcf.py new file mode 100755 index 0000000..a0d7ea0 --- /dev/null +++ b/ihex2rcf.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python + +import sys +import optparse + +from intelhex import IntelHex + +parser = optparse.OptionParser() + +parser.add_option('-s', '--start', dest='start', + action='store', type='int', help='Starting hex address of RCF') + +parser.add_option('-l', '--length', dest='length', + action='store', type='int', help='Length of RCF in words') + +parser.add_option('-w', '--width', dest='width', + action='store', type='int', help='Word size in bits') + +parser.add_option('-d', '--default', dest='default', + action='store', type='int', help='Default word for unspecified addresses') + +(opt, args) = parser.parse_args() + + + +def binword(w, width=16): + """Return a width-length, left-zero-padded bit string binary representation + of the integer w.""" + b = bin(w) + b = b.lstrip('0b') + return ('0' * (width - len(b))) + b + + +nbytes = (opt.width // 8) * opt.length +bytewidth = opt.width // 8 + +h = IntelHex(args[0]) + +#padding is *per byte* here, we need complete words and are specifying the +#default *word*. This lets us detect the missing values +h.padding = None + + +# dump all the ROM addresses +for addr in range(opt.start, (opt.start + opt.length), bytewidth): + word = 0 + bites = [h[a] is None for a in range(addr, addr+bytewidth)] + + if all(bites): + word = opt.default + elif any(bites): + raise Exception('Bytes must be specified for a complete word') + else: + for b in range(bytewidth): + word += h[addr + b] << (8*b) + + print binword(word) + diff --git a/msp4th/Makefile b/msp4th/Makefile index d20de5e..6ca941d 100644 --- a/msp4th/Makefile +++ b/msp4th/Makefile @@ -10,6 +10,9 @@ # SHELL = /bin/bash +DEFINE ?= +LDSCRIPT ?= ldscript_ns430 + TARGET = main #MCU = msp430f5529 MCU = msp2 @@ -31,13 +34,15 @@ INCLUDES = -I. #CFLAGS = -mmcu=$(MCU) -Werror -Wall -Wunused -mendup-at=main $(INCLUDES) #CFLAGS = -mmcu=$(MCU) -g -Os -Werror -Wall -Wunused $(INCLUDES) #CFLAGS = -mmcu=$(MCU) -g -Os -Werror -Wall -Wunused $(INCLUDES) -CFLAGS = -mcpu=$(CPU) -mmpy=$(MPY) -mivcnt=$(IVCNT) -g -Os -Werror -Wall -Wunused $(INCLUDES) +CFLAGS = $(DEFINE) -mcpu=$(CPU) -mmpy=$(MPY) -mivcnt=$(IVCNT) -g -Os -Werror -Wall -Wunused $(INCLUDES) #ASFLAGS = -mmcu=$(MCU) -x assembler-with-cpp -Wa,-gstabs #ASFLAGS = -mmcu=$(MCU) -Wall -Wunused -mendup-at=main $(INCLUDES) #ASFLAGS = -mmcu=$(MCU) -g -Os -Wall -Wunused $(INCLUDES) -ASFLAGS = -mcpu=$(CPU) -mmpy=$(MPY) -mivcnt=$(IVCNT) -g -Os -Wall -Wunused $(INCLUDES) +ASFLAGS = $(DEFINE) -mcpu=$(CPU) -mmpy=$(MPY) -mivcnt=$(IVCNT) -g -Os -Wall -Wunused $(INCLUDES) #LDFLAGS = -mmcu=$(MCU) -Wl,-Map=$(TARGET).map -T ldscript_ns430 -LDFLAGS = -mcpu=$(CPU) -mmpy=$(MPY) -mivcnt=$(IVCNT) -Wl,-Map=$(TARGET).map -T ldscript_ns430 +#LDFLAGS = -mcpu=$(CPU) -mmpy=$(MPY) -mivcnt=$(IVCNT) -Wl,-Map=$(TARGET).map -T ldscript_ns430 +LDFLAGS = $(DEFINE) -mcpu=$(CPU) -mmpy=$(MPY) -mivcnt=$(IVCNT) -Wl,-Map=$(TARGET).map -T $(LDSCRIPT) + ######################################################################################## CC = msp430-gcc LD = msp430-ld @@ -59,7 +64,7 @@ MV = mv DEPEND = $(SOURCES:.c=.d) # all the object files -OBJECTS = $(SOURCES:.c=.o) $(ASMS:.s=.o) +OBJECTS = $(SOURCES:.c=.o) # all asm files ASSEMBLYS = $(SOURCES:.c=.lst) @@ -67,6 +72,9 @@ ASSEMBLYS = $(SOURCES:.c=.lst) #all: $(TARGET).elf $(TARGET).hex $(TARGET).txt all: $(TARGET).elf $(TARGET).hex $(TARGET).xout $(ASSEMBLYS) +#we .include this, so it doesn't make it to the auto-generated dependencies +main.o: flashboot.s + $(TARGET).elf: $(OBJECTS) @echo "Linking $@" $(CC) $(OBJECTS) $(LDFLAGS) $(LIBS) -o $@ @@ -121,6 +129,10 @@ endif @echo "Generating dependencies $@ from $<" $(CC) -M ${CFLAGS} $< >$@ +bootrom.rcf: $(SOURCES) flashboot.s + $(MAKE) -B DEFINE=-DBOOTROM LDSCRIPT=ldscript_ns430_bootrom all + ../ihex2rcf.py --width=16 --start=0x3000 --length=0x1000 --default=0x0000 main.hex > $@ + .PHONY: flash flash: $(TARGET).hex ./flash.py $(ERASE) $(TARGET).hex diff --git a/msp4th/flashboot.s b/msp4th/flashboot.s index 1f84f46..b673c16 100644 --- a/msp4th/flashboot.s +++ b/msp4th/flashboot.s @@ -13,39 +13,6 @@ mov #StackStart,r1 dint - -; NOTE: we wakeup the flash chip (M25PE80) now to ensure we allow the -; requisite 30us for wakeup from deep sleep into idle/active mode. -;set PA(0) = 0 and enable output -;(should be) wired to flash /CS pin - mov #1, &PAOUT - mov #1, &PAOEN - -;enable peripherals: -; MISO0 -; MOSI0 -; SCLK0 -; output pins MOSI0 and SCLK0 are hard-wired as outputs -; when in peripheral mode, no need to change PAOUT - mov #0x000e,&PAPER - -;enable SPI0 -; set CPOL,CPHA = 1,1 -; 8-bit transfers - mov #0x0070,&SPI0_CR -;bring flash /CS pin low - bic #1, &PAOUT -;release flash from deep sleep - mov #0xab00,&SPI0_TDR -; wait until command done sending -1: - bit #1, &SPI0_SR - jz 1b -;now use 16-bit transfers - mov #0x00f0,&SPI0_CR -;de-select flash /CS - bis #1, &PAOUT - /* * old code. * I (Dan) do not quite fully understand what's going on. @@ -98,42 +65,96 @@ ; PA.7 low -> continue into default msp4th interpreter aka main() ; PA.7 high -> copy code from flash bit #0x0080,&PADSR - jz 8f ;#ContinueMain + jz 9f ;#ContinueMain + + +; NOTE: the flash chip (M25PE80) requires 30us for wakeup from +; deep sleep into idle/active mode. +;set PA(0) = 0 and enable output +;(should be) wired to flash /CS pin + mov #1, &PAOUT + mov #1, &PAOEN + +;enable peripherals: +; MISO0 +; MOSI0 +; SCLK0 +; output pins MOSI0 and SCLK0 are hard-wired as outputs +; when in peripheral mode, no need to change PAOUT + mov #0x000e,&PAPER + +;enable SPI0 +;clear status (any r/w) + mov #0, &SPI0_SR +; set CPOL,CPHA = 1,1 +; 8-bit transfers + mov #0x0070,&SPI0_CR +;bring flash /CS pin low + bic #1, &PAOUT +;release flash from deep sleep + mov #0xab00,&SPI0_TDR +; wait until command done sending +1: + bit #2, &SPI0_SR + jz 1b +;de-select flash /CS + bis #1, &PAOUT +;now use 16-bit transfers + mov #0x00f0,&SPI0_CR + +;delay for a bit, the flash needs minimum 30us to arrive in active/idle mode + mov #0xffff, r5 +2: + dec r5 + jnz 2b ;CopyFromFlash: ;setup CRC mov #0, &CRCINIRES + + +/* ;check state of PA.9 (aka I2C SCL) ;r13 holds the flag ; PA.9 low -> do not byteswap ; PA.9 high -> byteswap words from flash clr r13 bit #0x0200,&PADSR - jz 2f + jz 3f mov #1, r13 -2: +3: +*/ + ;r7 holds start of RAM address ;r8 (end of RAM)+1 -; mov #RAMStart,r7 - mov #0x6000,r7 +.ifdef BOOTROM + mov #RAMStart,r7 mova #(RAMStart+RAMSize),r8 +.else +;testing bootrom in RAM + mov #0x6000,r7 + mova #0xff00,r8 +.endif ;select flash /CS line bic #1, &PAOUT ;flash command 0x03 - read data bytes ; 00 - address MSB ; r7 - address low word (=RAMStart) mov #0x0300,&SPI0_TDR -; mov r7, &SPI0_TDR +.ifdef BOOTROM + mov r7, &SPI0_TDR +.else mov #0x4000,&SPI0_TDR +.endif ;wait for transmissions to finish -3: +4: bit #1, &SPI0_SR - jz 3b + jz 4b ;send 0x0000 to flash mov #0, &SPI0_TDR -4: +5: bit #1, &SPI0_SR - jz 4b + jz 5b ;send second 0x0000 to flash mov #0, &SPI0_TDR ;clear status register (any r/w does so) @@ -141,20 +162,25 @@ ;MainLoop1: ;wait for return word -5: +6: bit #4, &SPI0_SR - jz 5b + jz 6b ;store received word mov &SPI0_RDR,r5 ;send another 0x0000 to SPI mov #0, &SPI0_TDR -;?swap bytes? - tst r13 - jz 6f ;#SPINoSwap +;always swap bytes read from flash, consequences are: +; -memory layout in flash matches ihex file (little endian) +; -flash reads out bytes in address order +; -SPI reads as MSB first +; -therefore, the low-order byte of a word ends up in the high byte of a +; 16-bit read operation +; -hence we swap the bytes +; +; this is useful to know when writing from the ns430 to flash +; --> swap before 16-bit sends AND swap after 16-bit reads swpb r5 -;SPINoSwap: -6: ;copy received word to RAM address in r7 (ini=RAMStart) mov r5, 0(r7) ;compute CRC of data @@ -162,11 +188,12 @@ mov @r7+, &CRCDI ;?reached end of RAM? cmpa r7, r8 - jnz 5b ;#MainLoop1 + jnz 6b ;#MainLoop1 ;wait for last transmission to finish +7: bit #2, &SPI0_SR - jz $-4 + jz 7b ;deselect flash /CS line bis #1, &PAOUT @@ -179,21 +206,25 @@ ;flash command: deep power down mov #0xb900,&SPI0_TDR ;wait for completion -;deselect flash /CS line -7: +8: bit #2, &SPI0_SR - jz 7b - bis #1, &PAOUT + jz 8b +;deselect flash /CS line + bis #1, &PAOUT ;disable PA peripherals mov #0, &PAPER ;disable PA output drivers mov #0, &PAOEN -;execute user code starting at address pointed to by 0xfffe -; br &0xfffe +.ifdef BOOTROM + ;execute user code starting at address pointed to by 0xfffe + br &0xfffe +.else + ;fall-through the jump into the msp4th interpreter +.endif ;ContinueMain -8: +9: ; syntax from: git://github.com/vim-scripts/msp.vim.git ; vim: ft=msp diff --git a/msp4th/ldscript_ns430_bootrom b/msp4th/ldscript_ns430_bootrom new file mode 100644 index 0000000..c52562d --- /dev/null +++ b/msp4th/ldscript_ns430_bootrom @@ -0,0 +1,340 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-msp430") +OUTPUT_ARCH("msp430") +MEMORY { + sfr : ORIGIN = 0x0000, LENGTH = 0x0010 + peripheral_8bit : ORIGIN = 0x0010, LENGTH = 0x00f0 + peripheral_16bit : ORIGIN = 0x0100, LENGTH = 0x0100 + + ram (wx) : ORIGIN = 0x4000, LENGTH = 0xbfe0 + rom (rx) : ORIGIN = 0x3000, LENGTH = 0x1000 + + vectors : ORIGIN = 0xffc0, LENGTH = 64 + + /* Remaining banks are absent */ + bsl : ORIGIN = 0x0000, LENGTH = 0x0000 + infomem : ORIGIN = 0x0000, LENGTH = 0x0000 + infob : ORIGIN = 0x0000, LENGTH = 0x0000 + infoa : ORIGIN = 0x0000, LENGTH = 0x0000 + infoc : ORIGIN = 0x0000, LENGTH = 0x0000 + infod : ORIGIN = 0x0000, LENGTH = 0x0000 + ram2 (wx) : ORIGIN = 0x0000, LENGTH = 0x0000 + ram_mirror (wx) : ORIGIN = 0x0000, LENGTH = 0x0000 + usbram (wx) : ORIGIN = 0x0000, LENGTH = 0x0000 + far_rom : ORIGIN = 0x00000000, LENGTH = 0x00000000 +} + +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +/*REGION_ALIAS("REGION_FAR_ROM", far_rom);*/ +__WDTCTL = 0x0120; +__MPY = 0x0130; +__MPYS = 0x0132; +__MAC = 0x0134; +__MACS = 0x0136; +__OP2 = 0x0138; +__RESLO = 0x013A; +__RESHI = 0x013C; +__SUMEXT = 0x013E; + +SECTIONS +{ + /* Read-only sections, merged into text segment. */ + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .text : + { + . = ALIGN(2); + KEEP(*(.init .init.*)) + KEEP(*(.init0)) /* Start here after reset. */ + KEEP(*(.init1)) /* User definable. */ + KEEP(*(.init2)) /* Initialize stack. */ + KEEP(*(.init3)) /* Initialize hardware, user definable. */ + KEEP(*(.init4)) /* Copy data to .data, clear bss. */ + KEEP(*(.init5)) /* User definable. */ + KEEP(*(.init6)) /* C++ constructors. */ + KEEP(*(.init7)) /* User definable. */ + KEEP(*(.init8)) /* User definable. */ + KEEP(*(.init9)) /* Call main(). */ + KEEP(*(.fini9)) /* Falls into here after main(). User definable. */ + KEEP(*(.fini8)) /* User definable. */ + KEEP(*(.fini7)) /* User definable. */ + KEEP(*(.fini6)) /* C++ destructors. */ + KEEP(*(.fini5)) /* User definable. */ + KEEP(*(.fini4)) /* User definable. */ + KEEP(*(.fini3)) /* User definable. */ + KEEP(*(.fini2)) /* User definable. */ + KEEP(*(.fini1)) /* User definable. */ + KEEP(*(.fini0)) /* Infinite loop after program termination. */ + KEEP(*(.fini .fini.*)) + . = ALIGN(2); + __ctors_start = . ; + KEEP(*(.ctors)) + __ctors_end = . ; + __dtors_start = . ; + KEEP(*(.dtors)) + __dtors_end = . ; + . = ALIGN(2); + *(.text .text.* .gnu.linkonce.t.*) + . = ALIGN(2); + } > REGION_TEXT + .rodata : + { + . = ALIGN(2); + *(.rodata .rodata.* .gnu.linkonce.r.*) + . = ALIGN(2); + } > REGION_TEXT + _etext = .; /* Past last read-only (loadable) segment */ + .data : + { + . = ALIGN(2); + PROVIDE (__data_start = .) ; + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN(2); + _edata = . ; /* Past last read-write (loadable) segment */ + } > REGION_DATA AT > REGION_TEXT + PROVIDE (__data_load_start = LOADADDR(.data) ); + PROVIDE (__data_size = SIZEOF(.data) ); + .bss : + { + PROVIDE (__bss_start = .) ; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(2); + PROVIDE (__bss_end = .) ; + } > REGION_DATA + PROVIDE (__bss_size = SIZEOF(.bss) ); + .noinit : + { + PROVIDE (__noinit_start = .) ; + *(.noinit .noinit.*) + . = ALIGN(2); + PROVIDE (__noinit_end = .) ; + } > REGION_DATA + . = ALIGN(2); + _end = . ; /* Past last write (loadable) segment */ + .infomem : + { + *(.infomem) + . = ALIGN(2); + *(.infomem.*) + } > infomem + .infomemnobits : + { + *(.infomemnobits) + . = ALIGN(2); + *(.infomemnobits.*) + } > infomem + .infoa : + { + *(.infoa .infoa.*) + } > infoa + .infob : + { + *(.infob .infob.*) + } > infob + .infoc : + { + *(.infoc .infoc.*) + } > infoc + .infod : + { + *(.infod .infod.*) + } > infod + .vectors : + { + PROVIDE (__vectors_start = .) ; + KEEP(*(.vectors*)) + _vectors_end = . ; + } > vectors + /* + .fartext : + { + . = ALIGN(2); + *(.fartext) + . = ALIGN(2); + *(.fartext.*) + _efartext = .; + } > REGION_FAR_ROM + */ + /* Stabs for profiling information*/ + .profiler 0 : { *(.profiler) } + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + PROVIDE (__stack = ORIGIN(ram) + LENGTH(ram)); + PROVIDE (__data_start_rom = _etext); + PROVIDE (__data_end_rom = _etext + SIZEOF (.data)); +} +__PC_AFTER_RESET = 0x3000; +__CRCDI = 0x0000; +__CRCDI_L = 0x0000; +__CRCDI_H = 0x0001; +__CRCDIRB = 0x0002; +__CRCDIRB_L = 0x0002; +__CRCDIRB_H = 0x0002; +__CRCINIRES = 0x0004; +__CRCINIRES_L = 0x0004; +__CRCINIRES_H = 0x0005; +__CRCRESR = 0x0006; +__CRCRESR_L = 0x0006; +__CRCRESR_H = 0x0007; +__MPY = 0x0130; +__MPYS = 0x0132; +__MAC = 0x0134; +__MACS = 0x0136; +__OP2 = 0x0138; +__RESLO = 0x013a; +__RESHI = 0x013c; +__SUMEXT = 0x013e; +__AES_CR = 0x0400; +__AES_SR = 0x0402; +__AES_STATE = 0x0410; +__AES_STATE_SIZE = 0x0010; +__AES_KEY = 0x0700; +__AES_KEY_SIZE = 0x0020; +__AES_EXPKEY = 0x0720; +__AES_EXPKEY_SIZE = 0x00e0; +__PADSR = 0x1a00; +__PBDSR = 0x1a02; +__PAOEN = 0x1a04; +__PBOEN = 0x1a06; +__PAOUT = 0x1a08; +__PBOUT = 0x1a0a; +__PAPER = 0x1a0c; +__PBPER = 0x1a0e; +__PAIER = 0x1a10; +__PBIER = 0x1a12; +__PAIMR = 0x1a14; +__PBIMR = 0x1a16; +__PAPUE = 0x1a18; +__PBPUE = 0x1a1a; +__PBTSD = 0x1a1c; +__PBPSR = 0x1a1e; +__PAOCEN = 0x1a20; +__PBOCEN = 0x1a22; +__TMR0_CR = 0x1c00; +__TMR0_SR = 0x1c02; +__TMR0_CNT = 0x1c04; +__TMR0_RA = 0x1c06; +__TMR0_RB = 0x1c08; +__TMR0_RC = 0x1c0a; +__TMR0_CAP0 = 0x1c0c; +__TMR0_CAP1 = 0x1c0e; +__TMR1_CR = 0x1c10; +__TMR1_SR = 0x1c12; +__TMR1_CNT = 0x1c14; +__TMR1_RA = 0x1c16; +__TMR1_RB = 0x1c18; +__TMR1_RC = 0x1c1a; +__TMR1_CAP0 = 0x1c1c; +__TMR1_CAP1 = 0x1c1e; +__TMR2_CR = 0x1e00; +__TMR2_SR = 0x1e02; +__TMR2_CNT = 0x1e04; +__TMR2_RA = 0x1e06; +__TMR2_RB = 0x1e08; +__TMR2_RC = 0x1e0a; +__TMR2_CAP0 = 0x1e0c; +__TMR2_CAP1 = 0x1e0e; +__TMR3_CR = 0x1e10; +__TMR3_SR = 0x1e12; +__TMR3_CNT = 0x1e14; +__TMR3_RA = 0x1e16; +__TMR3_RB = 0x1e18; +__TMR3_RC = 0x1e1a; +__TMR3_CAP0 = 0x1e1c; +__TMR3_CAP1 = 0x1e1e; +__SPI0_CR = 0x2000; +__SPI0_RDR = 0x2002; +__SPI0_TDR = 0x2004; +__SPI0_SR = 0x2006; +__SPI1_CR = 0x2008; +__SPI1_RDR = 0x200a; +__SPI1_TDR = 0x200c; +__SPI1_SR = 0x200e; +__UART0_CR = 0x2200; +__UART0_BCR = 0x2202; +__UART0_SR = 0x2204; +__UART0_RDR = 0x2206; +__UART0_TDR = 0x2208; +__UART1_CR = 0x2210; +__UART1_BCR = 0x2212; +__UART1_SR = 0x2214; +__UART1_RDR = 0x2216; +__UART1_TDR = 0x2218; +__ADC_CR = 0x2400; +__GPIN0 = 0x2402; +__GPIN1 = 0x2404; +__GPOUT0 = 0x2406; +__GPOUT1 = 0x2408; +__GPOUT2 = 0x240a; +__GPOUT3 = 0x240c; +__I2CM_CR = 0x2a00; +__I2CM_TCFG = 0x2a02; +__I2CM_SR = 0x2a04; +__I2CM_WCR = 0x2a06; +__I2CM_TDR_ST = 0x2a08; +__I2CM_TDR = 0x2a0a; +__I2CM_TDR_SP = 0x2a0c; +__I2CM_RDR = 0x2a0e; +__I2CS_CR = 0x2a10; +__I2CS_SR = 0x2a12; +__I2CS_TDR = 0x2a14; +__I2CS_RDR = 0x2a16; +__ROMStart = 0x3000; +__ROMSize = 0x0800; +__RAMStart = 0x4000; +__RAMSize = 0xc000; diff --git a/msp4th/main.c b/msp4th/main.c index 19c739f..6a2175b 100644 --- a/msp4th/main.c +++ b/msp4th/main.c @@ -14,7 +14,8 @@ /* - * Re-define the startup/reset behavior to this. + * Re-define the startup/reset behavior to this. GCC normally uses this + * opportunity to initialize all variables (bss) to zero. * * By doing this, we take all initialization into our own hands. * @@ -54,6 +55,21 @@ static void __inline__ eint(void){ +void init_uart(void) +{ + int16_t tmp; + // chip setup for UART0 use + PAPER = 0x0030; + PAOUT = 0x0000; + PAOEN = 0x0010; // set data direction registers + + UART0_BCR = UART_BCR(DEVBOARD_CLOCK, BAUDRATE); + UART0_CR = UARTEn; + + // a read clears the register -- ready for TX/RX + tmp = UART0_SR; +} + @@ -79,26 +95,14 @@ int main(void){ * where the label is searched for forwards or backwards according to the * suffix Nf or Nb. */ +#ifdef BOOTROM + asm(".set BOOTROM, 1"); +#endif asm(".include \"flashboot.s\""); - int16_t tmp; dint(); - - - // chip setup for UART0 use - PAPER = 0x0030; - PAOUT = 0x0000; - PAOEN = 0x0010; // set data direction registers - - UART0_BCR = UART_BCR(DEVBOARD_CLOCK, BAUDRATE); - UART0_CR = UARTEn; - - // a read clears the register -- ready for TX/RX - tmp = UART0_SR; - - uart_puts((str_t *)"in main()!"); - + init_uart(); /* * Startup and run msp4th interp -- 2.25.1