From b4f8289ff4e0aa4dbbd53705a15cf03e67bf4dc7 Mon Sep 17 00:00:00 2001 From: Dan White Date: Sat, 28 Jan 2012 19:23:21 -0600 Subject: [PATCH] notes --- sch-pcb/pinout-notes.otl | 108 +++++++++++++++++++-------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/sch-pcb/pinout-notes.otl b/sch-pcb/pinout-notes.otl index 7a4a4d1..016708f 100644 --- a/sch-pcb/pinout-notes.otl +++ b/sch-pcb/pinout-notes.otl @@ -51,7 +51,7 @@ Power [X] 100% By-PS-Domain [X] 100% DCDC - supplies all others : do not use - [X] 100% LDO0 - Digital + [X] 100% LDO0 - wb430 : ADP323 triple adj LDO with EN : Needs separate >= 2.5 Vbias [X] Vdd_ns430 - core 1.2 V @@ -62,7 +62,7 @@ Power [X] wb430 DVDD_OSCIO [X] AVdd_atoi - AtoI analog 2.5V [X] wb430 AVDD Analog - [X] 100% LDO1 - AtoI, analog + [X] 100% LDO1 - Peripheral, digital : ADP323 triple adj LDO with EN : Needs separate >= 2.5 Vbias [X] Vdd_digi - AtoI digital core 1.2 V @@ -84,7 +84,7 @@ Power Connections - [_] 0% ns430 + [_] 20% ns430 [_] Symbol [_] Footprint [_] 0% Digital Pins @@ -137,64 +137,64 @@ Connections : to flash [_] 18- PA0 / CS_flash : to flash - [_] 0% Analog Pins - [_] 0% Single OTA - [_] ota_slow - 2v4 logic - [_] ota_slowinv - 2v4 logic - [_] ota_biasa - current sink - [_] ota_biasb - current sink - [_] ota_biasccp - voltage bias - [_] ota_biasccn - voltage bias - [_] ota_ina - signal input - [_] ota_inb - signal input - [_] ota_cmi - signal input - [_] ota_out - signal output - [_] 0% AtoI Main Channels - [_] 0% Integrator Bias + [_] 83% Analog Pins + [X] 100% Single OTA + [X] ota_slow - 2v4 logic + [X] ota_slowinv - 2v4 logic + [X] ota_biasa - current sink + [X] ota_biasb - current sink + [X] ota_biasccp - voltage bias + [X] ota_biasccn - voltage bias + [X] ota_ina - signal input + [X] ota_inb - signal input + [X] ota_cmi - signal input + [X] ota_out - signal output + [_] 66% AtoI Main Channels + [_] 33% Integrator Bias [_] biasp - main current setting voltage : read only unless... [_] send to ADC [_] biasccp - cascode bias voltage : read only unless... [_] send to ADC - [_] biasR - resistance in bias loop generator + [X] biasR - resistance in bias loop generator : TODO expected R range : 2 resistors, bottom fixed and known C-V converter for ADC - [_] send to ADC - [_] 0% Mux Buffer Bias + [X] send to ADC + [_] 33% Mux Buffer Bias [_] buf_biasp - main current setting voltage : read only unless... [_] send to ADC [_] buf_biasccp - cascode bias voltage : read only unless... [_] send to ADC - [_] buf_biasR - resistance in bias loop generator + [X] buf_biasR - resistance in bias loop generator : TODO expected R range : 2 resistors, bottom fixed and known C-V converter for ADC - [_] send to ADC - [_] 0% Signal Inputs - [_] INA - diff signal - [_] from DAC - [_] INB - diff signal - [_] from DAC - [_] CMI - AREF analog "0" - [_] from AREF generator - [_] 0% Signal Outputs + [X] send to ADC + [X] 100% Signal Inputs + [X] INA - diff signal + [X] from DAC + [X] INB - diff signal + [X] from DAC + [X] CMI - AREF analog "0" + [X] from AREF generator + [X] 100% Signal Outputs : full AVDD-AVSS range - [_] mux0_outA - AtoI integrator mux/buffer output - [_] send to ADC - [_] mux0_outB - AtoI integrator mux/buffer output - [_] send to ADC - [_] arb_out0 - Arb output(0) direct - [_] send to ADC - [_] arb_out1 - Arb output(1) direct - [_] send to ADC - [_] mux1_outA - Arb mux/buffer output - [_] send to ADC - [_] mux1_outB - Arb mux/buffer output - [_] send to ADC + [X] mux0_outA - AtoI integrator mux/buffer output + [X] send to ADC + [X] mux0_outB - AtoI integrator mux/buffer output + [X] send to ADC + [X] arb_out0 - Arb output(0) direct + [X] send to ADC + [X] arb_out1 - Arb output(1) direct + [X] send to ADC + [X] mux1_outA - Arb mux/buffer output + [X] send to ADC + [X] mux1_outB - Arb mux/buffer output + [X] send to ADC - [_] 16% cc430f5137 + [_] 5% cc430f5137 : on board [_] Symbol [_] Footprint @@ -265,7 +265,7 @@ Connections [_] 20- P3.1/TA0CCR0A [_] 21- P3.0/CBOUT0/TA0CLK [_] 23- P2.7/ADC12CLK/DMAE0 - [_] 47% ADC0 - shared SPI bus + [_] 28% ADC0 - shared SPI bus : ADS8201 (sampled from TI) : QFN-24 : needs Vref @@ -309,7 +309,7 @@ Connections : PCB footprints for RC filter or short-to-ADCIN [_] PGAREF - set to Vanalog/2 for signed codes : switchable between gnd and Vref/2 - [_] 4% DAC0 - shared SPI bus + [_] 2% DAC0 - shared SPI bus : DAC8568 (sampled from TI) : TSSOP-16 : 8ch 16bit 2.7 Vmin @@ -320,13 +320,13 @@ Connections [_] SPI1 on ns430 [_] USCI_A0 or USCI_B0 on cc430 [_] 0% Output Signals - [_] x - biasR tuning - [_] x - buf_biasR tuning - [_] x - - [_] x - - [_] x - - [_] x - - [_] x - + [_] 0 - biasR tuning + [_] 1 - buf_biasR tuning + [_] 2 - INA + [_] 3 - INB + [_] 4 - CMI (thru jumper) + [_] x - ota_biasa + [_] x - ota_biasb [_] x - [_] 12% Pins [_] 1 - /LDAC - load DACs @@ -346,7 +346,7 @@ Connections [X] 14- GND [_] 15- DIN - SPI MOSI [_] 16- SCLK - SPI clock - [_] 65% DigiPot0 - shared I2C bus + [_] 43% DigiPot0 - shared I2C bus : AD5242 (sampled from ADI) : 1M 256tap I2C pot 2.7 Vmin : TSSOP-16 @@ -416,7 +416,7 @@ Connections [_] 14- B2 - pot2 bottom [_] 15- W2 - pot2 wiper [_] 16- A2 - pot2 top - [_] 18% M25PExx flash + [_] 9% M25PExx flash [_] Symbol [_] Footprint [_] 0% Control -- 2.25.1