From e840ebb916d287076cd8b1794b65256cffc74506 Mon Sep 17 00:00:00 2001 From: drowe67 Date: Tue, 18 Jun 2013 06:41:20 +0000 Subject: [PATCH] first pass at ADC record program, looks OK for DC & sine waves git-svn-id: https://svn.code.sf.net/p/freetel/code@1322 01035d8c-6547-0410-b346-abe4f91aad63 --- codec2-dev/stm32/src/dac_play.c | 10 +- codec2-dev/stm32/src/stm32f4_adc.c | 414 +++-------------------------- 2 files changed, 47 insertions(+), 377 deletions(-) diff --git a/codec2-dev/stm32/src/dac_play.c b/codec2-dev/stm32/src/dac_play.c index aa69f332..979b30d5 100644 --- a/codec2-dev/stm32/src/dac_play.c +++ b/codec2-dev/stm32/src/dac_play.c @@ -33,25 +33,25 @@ int main(void) { short buf[N]; - FILE *fin; + FILE *fplay; dac_open(); while(1) { - fin = fopen("stm_in.raw", "rb"); - if (fin == NULL) { + fplay = fopen("stm_in.raw", "rb"); + if (fplay == NULL) { printf("Error opening input file: stm_in.raw\n\nTerminating....\n"); exit(1); } printf("Starting!\n"); - while(fread(buf, sizeof(short), N, fin) == N) { + while(fread(buf, sizeof(short), N, fplay) == N) { while(dac_write(buf, N) == -1); } printf("Finished!\n"); - fclose(fin); + fclose(fplay); } /* let FIFO empty */ diff --git a/codec2-dev/stm32/src/stm32f4_adc.c b/codec2-dev/stm32/src/stm32f4_adc.c index 6bc93b58..90c1ddd9 100644 --- a/codec2-dev/stm32/src/stm32f4_adc.c +++ b/codec2-dev/stm32/src/stm32f4_adc.c @@ -15,7 +15,9 @@ + fifos + work out a way to unit test [ ] ADC working at same time as DAC - + [ ] remove (or make optional) the TIM_Config() code that sends PWM output to pins + [ ] check comments still valid + \*---------------------------------------------------------------------------*/ /* @@ -69,7 +71,14 @@ uint16_t aSRC_Buffer[3] = {0, 0, 0}; void Timer1Config(); void adc_configure(); +#define REC_TIME_SECS 30 +#define N 2000 +#define FS 16000 + int main(void){ + short buf[N]; + FILE *frec; + int i, bufs; DMA2_Stream0_fifo = fifo_create(FIFO_SZ); assert(DMA2_Stream0_fifo != NULL); @@ -77,17 +86,30 @@ int main(void){ Timer1Config(); adc_configure(); ADC_SoftwareStartConv(ADC1); - while(1){ + + frec = fopen("stm_out.raw", "wb"); + if (frec == NULL) { + printf("Error opening input file: stm_out.raw\n\nTerminating....\n"); + exit(1); + } + bufs = FS*REC_TIME_SECS/N; + + for(i=0; i TIM1CLK = 2 * (HCLK / 2) = HCLK = SystemCoreClock - - TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock - SystemCoreClock is set to 168 MHz for STM32F4xx devices. - - The objective is to configure TIM1 channel 3 to generate complementary PWM - signal with a frequency equal to 17.57 KHz: - - TIM1_Period = (SystemCoreClock / 17570) - 1 - and a variable duty cycle that is changed by the DMA after a specific number of - Update DMA request. - - The number of this repetitive requests is defined by the TIM1 Repetion counter, - each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new - value defined by the aSRC_Buffer. - - Note: - SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file. - Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() - function to update SystemCoreClock variable value. Otherwise, any configuration - based on this variable will be incorrect. - -----------------------------------------------------------------------------*/ - - /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */ - uhTimerPeriod = (SystemCoreClock / 17570 ) - 1; - /* Compute CCR1 value to generate a duty cycle at 50% */ - aSRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (uhTimerPeriod - 1)) / 10); - /* Compute CCR1 value to generate a duty cycle at 37.5% */ - aSRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (uhTimerPeriod - 1)) / 1000); - /* Compute CCR1 value to generate a duty cycle at 25% */ - aSRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (uhTimerPeriod - 1)) / 100); - - /* TIM1 Peripheral Configuration -------------------------------------------*/ - /* TIM1 clock enable */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); - - /* Time Base configuration */ - TIM_TimeBaseStructure.TIM_Prescaler = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseStructure.TIM_Period = uhTimerPeriod; - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_RepetitionCounter = 3; - - TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); - - /* Channel 3 Configuration in PWM mode */ - TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; - TIM_OCInitStructure.TIM_Pulse = aSRC_Buffer[0]; - TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; - TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low; - TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set; - TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset; - - TIM_OC3Init(TIM1, &TIM_OCInitStructure); - - /* Enable preload feature */ - TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable); - - /* TIM1 counter enable */ - TIM_Cmd(TIM1, ENABLE); - - /* DMA enable*/ - DMA_Cmd(DMA2_Stream6, ENABLE); - - /* TIM1 Update DMA Request enable */ - TIM_DMACmd(TIM1, TIM_DMA_CC3, ENABLE); - - /* Main Output Enable */ - TIM_CtrlPWMOutputs(TIM1, ENABLE); -} - -/** - * @brief ADC3 channel07 with DMA configuration - * @note This function Configure the ADC peripheral - 1) Enable peripheral clocks - 2) DMA2_Stream0 channel2 configuration - 3) Configure ADC Channel7 pin as analog input - 4) Configure ADC3 Channel7 - * @param None - * @retval None - */ -static void ADC_Config(void) -{ - ADC_InitTypeDef ADC_InitStructure; - ADC_CommonInitTypeDef ADC_CommonInitStructure; - DMA_InitTypeDef DMA_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable ADCx, DMA and GPIO clocks ****************************************/ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); - RCC_AHB1PeriphClockCmd(ADCx_CHANNEL_GPIO_CLK, ENABLE); - RCC_APB2PeriphClockCmd(ADCx_CLK, ENABLE); - - - /* DMA2 Stream0 channel2 configuration **************************************/ - DMA_InitStructure.DMA_Channel = DMA_CHANNELx; - DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADCx_DR_ADDRESS; - DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&uhADCxConvertedValue; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; - DMA_InitStructure.DMA_BufferSize = 1; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; - DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; - DMA_InitStructure.DMA_Priority = DMA_Priority_High; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(DMA_STREAMx, &DMA_InitStructure); - DMA_Cmd(DMA_STREAMx, ENABLE); - - /* Configure ADC3 Channel7 pin as analog input ******************************/ - GPIO_InitStructure.GPIO_Pin = GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIO_PORT, &GPIO_InitStructure); - - /* ADC Common Init **********************************************************/ - ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; - ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2; - ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; - ADC_CommonInit(&ADC_CommonInitStructure); - - /* ADC3 Init ****************************************************************/ - ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b; - ADC_InitStructure.ADC_ScanConvMode = DISABLE; - ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; - ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStructure.ADC_NbrOfConversion = 1; - ADC_Init(ADCx, &ADC_InitStructure); - - /* ADC3 regular channel7 configuration *************************************/ - ADC_RegularChannelConfig(ADCx, ADC_CHANNEL, 1, ADC_SampleTime_3Cycles); - - /* Enable DMA request after last transfer (Single-ADC mode) */ - ADC_DMARequestAfterLastTransferCmd(ADCx, ENABLE); - - /* Enable ADC3 DMA */ - ADC_DMACmd(ADCx, ENABLE); - - /* Enable ADC3 */ - ADC_Cmd(ADCx, ENABLE); -} - -void Timer1Config() { - - /* TIM Configuration */ - - TIM_Config(); - - /* TIM1 DMA Transfer example ------------------------------------------------- - - TIM1 input clock (TIM1CLK) is set to 2 * APB2 clock (PCLK2), since APB2 - prescaler is different from 1. - TIM1CLK = 2 * PCLK2 - PCLK2 = HCLK / 2 - => TIM1CLK = 2 * (HCLK / 2) = HCLK = SystemCoreClock - - TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock - SystemCoreClock is set to 168 MHz for STM32F4xx devices. - - The objective is to configure TIM1 channel 3 to generate complementary PWM - signal with a frequency equal to 17.57 KHz: - - TIM1_Period = (SystemCoreClock / 17570) - 1 - and a variable duty cycle that is changed by the DMA after a specific number of - Update DMA request. - - The number of this repetitive requests is defined by the TIM1 Repetion counter, - each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new - value defined by the aSRC_Buffer. - - Note: - SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file. - Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() - function to update SystemCoreClock variable value. Otherwise, any configuration - based on this variable will be incorrect. - -----------------------------------------------------------------------------*/ - - /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */ - uhTimerPeriod = (SystemCoreClock / 17570 ) - 1; - /* Compute CCR1 value to generate a duty cycle at 50% */ - aSRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (uhTimerPeriod - 1)) / 10); - /* Compute CCR1 value to generate a duty cycle at 37.5% */ - aSRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (uhTimerPeriod - 1)) / 1000); - /* Compute CCR1 value to generate a duty cycle at 25% */ - aSRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (uhTimerPeriod - 1)) / 100); - - /* TIM1 Peripheral Configuration -------------------------------------------*/ - /* TIM1 clock enable */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); - - /* Time Base configuration */ - TIM_TimeBaseStructure.TIM_Prescaler = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseStructure.TIM_Period = uhTimerPeriod; - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_RepetitionCounter = 3; - - TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); - - /* Channel 3 Configuration in PWM mode */ - TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; - TIM_OCInitStructure.TIM_Pulse = aSRC_Buffer[0]; - TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; - TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low; - TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set; - TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset; - - TIM_OC3Init(TIM1, &TIM_OCInitStructure); - - /* Enable preload feature */ - TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable); - - /* TIM1 counter enable */ - TIM_Cmd(TIM1, ENABLE); - - /* DMA enable*/ - DMA_Cmd(DMA2_Stream6, ENABLE); - - /* TIM1 Update DMA Request enable */ - TIM_DMACmd(TIM1, TIM_DMA_CC3, ENABLE); - - /* Main Output Enable */ - TIM_CtrlPWMOutputs(TIM1, ENABLE); -} - -/* DR: note I dont think any of this is needed, except perhaps to check - timer frequency */ - -/** - * @brief Configure the TIM1 Pins. - * @param None - * @retval None - */ -static void TIM_Config(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - DMA_InitTypeDef DMA_InitStructure; - - /* GPIOA and GPIOB clock enable */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB, ENABLE); - - /* GPIOA Configuration: Channel 3 as alternate function push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 ; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_TIM1); - - /* GPIOB Configuration: Channel 3N as alternate function push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_TIM1); - - /* DMA clock enable */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 , ENABLE); - - DMA_DeInit(DMA2_Stream6); - DMA_InitStructure.DMA_Channel = DMA_Channel_6; - DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(TIM1_CCR3_ADDRESS) ; - DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)aSRC_Buffer; - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_BufferSize = 3; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; - DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_HalfWord; - DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; - DMA_InitStructure.DMA_Priority = DMA_Priority_High; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - - DMA_Init(DMA2_Stream6, &DMA_InitStructure); -} -#endif -- 2.25.1