From ebaf9788ed03eb400c92a9beb05c03993d7e6b3c Mon Sep 17 00:00:00 2001 From: Dan White Date: Tue, 24 Jan 2012 15:00:16 -0600 Subject: [PATCH] WIP dev board pinout planning --- test-pcb/pinout-notes.otl | 250 +++++++++++++++++++++++--------------- 1 file changed, 151 insertions(+), 99 deletions(-) diff --git a/test-pcb/pinout-notes.otl b/test-pcb/pinout-notes.otl index 80ef6cd..8aa2649 100644 --- a/test-pcb/pinout-notes.otl +++ b/test-pcb/pinout-notes.otl @@ -1,85 +1,26 @@ -[_] 0% Analog pins - [_] 0% Single OTA - [_] ota_slow - 2v4 logic - [_] ota_slowinv - 2v4 logic - [_] ota_biasa - current sink - [_] ota_biasb - current sink - [_] ota_biasccp - voltage bias - [_] ota_biasccn - voltage bias - [_] ota_ina - signal input - [_] ota_inb - signal input - [_] ota_cmi - signal input - [_] ota_out - signal output - [_] 0% AtoI Main Channels - [_] 0% Integrator Bias - [_] biasp - main current setting voltage - : read only unless... - [_] send to ADC - [_] biasccp - cascode bias voltage - : read only unless... - [_] send to ADC - [_] biasR - resistance in bias loop generator - : TODO expected R range - : 2 resistors, bottom fixed and known C-V converter for ADC - [_] send to ADC - [_] 0% Mux Buffer Bias - [_] buf_biasp - main current setting voltage - : read only unless... - [_] send to ADC - [_] buf_biasccp - cascode bias voltage - : read only unless... - [_] send to ADC - [_] buf_biasR - resistance in bias loop generator - : TODO expected R range - : 2 resistors, bottom fixed and known C-V converter for ADC - [_] send to ADC - [_] 0% Signal Inputs - [_] INA - diff signal - [_] from DAC - [_] INB - diff signal - [_] from DAC - [_] CMI - AREF analog "0" - [_] from AREF generator - [_] 0% Signal Outputs - : full AVDD-AVSS range - [_] mux0_outA - AtoI integrator mux/buffer output - [_] send to ADC - [_] mux0_outB - AtoI integrator mux/buffer output - [_] send to ADC - [_] arb_out0 - Arb output(0) direct - [_] send to ADC - [_] arb_out1 - Arb output(1) direct - [_] send to ADC - [_] mux1_outA - Arb mux/buffer output - [_] send to ADC - [_] mux1_outB - Arb mux/buffer output - [_] send to ADC - -[_] % Digital Pins - Notes USCI_A0 on cc430 supports SPI, UART USCI_B0 on cc430 supports SPI, I2C After boot, r9 holds RAMER count Power - [_] 91% By-IC - [_] 50% wb430 - [_] 50% AtoI + [X] 100% By-IC + [X] 100% wb430 + [X] 100% AtoI [X] AVDD Analog 2.5V - [_] AVSS Analog gnd + [X] AVSS Analog gnd [X] VDD_atoi digital core 1.2V - [_] VSS_atoi digital core gnd - [_] 50% NS430 + [X] VSS_atoi digital core gnd + [X] 100% NS430 [X] DVDD_PadIO 2.5V - [_] DVDD_PadIO gnd + [X] DVDD_PadIO gnd [X] DVDD_OSCIO 2.5V - [_] DVSS_OSCIO gnd + [X] DVSS_OSCIO gnd [X] VDD_430 core 1.2V - [_] VSS_430 core gnd + [X] VSS_430 core gnd [X] VDD_osc core 1.2V - [_] VSS_osc core gnd + [X] VSS_osc core gnd [X] 100% cc430 Processor : PMMCOREV modes @@ -104,7 +45,6 @@ Power [X] 100% AD5242 - dual 100k pot (LDO) : DigiPot1 [X] 2.2 Vmin - [X] 100% By-PS-Domain [_] 0% DCDC - supplies all others [X] 100% LDO0 - Digital @@ -116,17 +56,17 @@ Power [X] DVdd_ns430 - Pad 2.5 V [X] wb430 DVDD_PadIO [X] wb430 DVDD_OSCIO - [X] Vdd_dev - cc430 1.8-3.6 V - [X] cc430 DVCC - [X] cc430 AVcc_RF - [X] cc430 AVcc + [X] AVdd_atoi - AtoI analog 2.5V + [X] wb430 AVDD Analog [X] 100% LDO1 - AtoI, analog : ADP323 triple adj LDO with EN : Needs separate >= 2.5 Vbias [X] Vdd_digi - AtoI digital core 1.2 V [X] wb430 VDD_atoi - [X] AVdd_atoi - AtoI analog 2.5V - [X] wb430 AVDD Analog + [X] Vdd_dev - cc430 1.8-3.6 V + [X] cc430 DVCC + [X] cc430 AVcc_RF + [X] cc430 AVcc [X] AVdd_dev - peripheral analog 2.7 V : full dev board - fixed at 2.7 V : ADC0 and DigiPotX may be 2.2 V for small board @@ -134,18 +74,18 @@ Power [X] ADC0 VA [X] DAC0 AVdd [X] DigiPot0 Vdd - [X] DigiPot0 Vdd + [X] DigiPot1 Vdd Connections [_] 0% ns430 - : SPI0 - flash - : SPI1 - AtoI digital - : UART0 - bootloader, comms - : UART1 - ??? - : I2C - DigiPots (biasR, LDO) [_] 0% Digital Pins + : SPI0 - flash + : SPI1 - AtoI digital + : UART0 - bootloader, comms + : UART1 - ??? + : I2C - DigiPots (biasR, LDO) [_] 94 - GPOut33 / CS1_mux (pad mux) [_] 95 - GPOut32 / CS1_conf (pad mux) [_] 96 - GPOut1 / MULT1 (pad mux) @@ -190,6 +130,134 @@ Connections : to flash [_] 18- PA0 / CS_flash : to flash + [_] 0% Analog Pins + [_] 0% Single OTA + [_] ota_slow - 2v4 logic + [_] ota_slowinv - 2v4 logic + [_] ota_biasa - current sink + [_] ota_biasb - current sink + [_] ota_biasccp - voltage bias + [_] ota_biasccn - voltage bias + [_] ota_ina - signal input + [_] ota_inb - signal input + [_] ota_cmi - signal input + [_] ota_out - signal output + [_] 0% AtoI Main Channels + [_] 0% Integrator Bias + [_] biasp - main current setting voltage + : read only unless... + [_] send to ADC + [_] biasccp - cascode bias voltage + : read only unless... + [_] send to ADC + [_] biasR - resistance in bias loop generator + : TODO expected R range + : 2 resistors, bottom fixed and known C-V converter for ADC + [_] send to ADC + [_] 0% Mux Buffer Bias + [_] buf_biasp - main current setting voltage + : read only unless... + [_] send to ADC + [_] buf_biasccp - cascode bias voltage + : read only unless... + [_] send to ADC + [_] buf_biasR - resistance in bias loop generator + : TODO expected R range + : 2 resistors, bottom fixed and known C-V converter for ADC + [_] send to ADC + [_] 0% Signal Inputs + [_] INA - diff signal + [_] from DAC + [_] INB - diff signal + [_] from DAC + [_] CMI - AREF analog "0" + [_] from AREF generator + [_] 0% Signal Outputs + : full AVDD-AVSS range + [_] mux0_outA - AtoI integrator mux/buffer output + [_] send to ADC + [_] mux0_outB - AtoI integrator mux/buffer output + [_] send to ADC + [_] arb_out0 - Arb output(0) direct + [_] send to ADC + [_] arb_out1 - Arb output(1) direct + [_] send to ADC + [_] mux1_outA - Arb mux/buffer output + [_] send to ADC + [_] mux1_outB - Arb mux/buffer output + [_] send to ADC + + [_] 0% cc430f5137 + : on board + [_] 0% Pins + RF + RFIO + [_] 29- RF_P + [_] 30- RF_N + RF OSC, bias + [_] 25- RF_Xi + [_] 26- RF_XOUT + [_] 33- RBIAS + GP IO / RF interrupt + [_] 12- P1.1/RFGDO2 + [_] 13- P1.0/RFGDO0 + [_] 15- P3.6/RFGDO1 + Comm + : UCA0 supports SPI, UART + : UCB0 supports SPI, I2C + [_] 4 - P1.7/UCA0CLK/UCB0STE + [_] 5 - P1.6/UCA0TXD/UCA0MOSI + [_] 6 - P1.5/UCA0RXD/UCA0MISO + [_] 9 - P1.4/UCB0CLK/UCA0STE + [_] 10- P1.3/UCB0MOSI/UCB0SDA + [_] 11- P1.2/UCB0MISO/UCB0SCL + Sys / JTAG / SpyBiWire + [_] 35- PJ.0/TDO + [_] 36- PJ.1/TDI/TCLK + [_] 37- PJ.2/TMS + [_] 38- PJ.3/TCK + [_] 39- TEST/SBWTCK + [_] 40- \_RST\_/NMI/SBWTDIO + Power + [_] 7 - VCORE + [_] 8 - DVCC + [_] 27- AVCC_RF + [_] 28- AVCC_RF + [_] 31- AVCC_RF + [_] 32- AVCC_RF + [_] 22- DVCC + [_] 34- GUARD + [_] 41- DVCC + [_] 42- AVSS + [_] 45- AVCC + [_] 49- VSS_EP + ADC12 / Comp / Ref + : x - arb_out0 ?? + : x - arb_out1 ?? + : - IVdd_ns430 + : - IDVdd_ns430 + : - IAVdd_atoi + : - IVdd_digi + : - IVdd_dev + : - IAVdd_dev + [_] 46- P2.5/SVMOUT/CB5/A5/VREF+/VeREF+ + [_] 47- P2.4/RTCCLK/CB4/A4/VREF-/VeREF- + [_] 48- P2.3/TA1CCR2A/CB3/A3 + [_] 1 - P2.2/TA1CCR1A/CB2/A2 + [_] 2 - P2.1/TA1CCR0A/CB1/A1 + [_] 3 - P2.0/CBOUT1/TA1CLK/CB0/A0 + Timing / GP + [_] 43- P5.1/XOUT + [_] 44- P5.0/Xi + [_] 14- P3.7/SMCLK + [_] 24- P2.6/ACLK + [_] 16- P3.5/TA0CCR4A + [_] 17- P3.4/TA0CCR3A + [_] 18- P3.3/TA0CCR2A + [_] 19- P3.2/TA0CCR1A + [_] 20- P3.1/TA0CCR0A + [_] 21- P3.0/CBOUT0/TA0CLK + [_] 23- P2.7/ADC12CLK/DMAE0 [_] 4% ADC0 - shared SPI bus : ADS8201 (sampled from TI) : QFN-24 @@ -232,23 +300,6 @@ Connections : PCB footprints for RC filter or short-to-ADCIN [_] PGAREF - set to Vanalog/2 for signed codes : switchable between gnd and Vref/2 - [_] 0% ADC1 - on cc430 - : pins shared with - : ref gen in/out - : comparator - : timerA1 - : RTC clock out - : SVM supply V monitor flag - x - biasp - x - biasccp - x - buf_biasp - x - buf_biasccp - x - arb_out0 ?? - x - arb_out1 ?? - - Idvdd_430 - - Ivdd_430 - - Ivdd_atoi - - Iavdd [_] 2% DAC0 - shared SPI bus : DAC8568 (sampled from TI) : TSSOP-16 @@ -350,3 +401,4 @@ Connections [_] 15- W2 - pot2 wiper [_] 16- A2 - pot2 top + -- 2.25.1