From f2e203c8ec0c5622fb7569062946d6f839dc6bdb Mon Sep 17 00:00:00 2001 From: Dan White Date: Sat, 2 Jun 2012 21:12:03 -0500 Subject: [PATCH] re-check dac-adc direct connection, good --- python-lib/mpsse-test.py | 14 +++++++++----- python-lib/usbio.py | 12 +++++++----- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/python-lib/mpsse-test.py b/python-lib/mpsse-test.py index 7a980cb..d449506 100755 --- a/python-lib/mpsse-test.py +++ b/python-lib/mpsse-test.py @@ -136,6 +136,7 @@ dac.vbias_core(100e-3) dac.vbias_buf(100e-3) # zero others +# part A already POR's to 0 but... for i in range(5, 8): dac.setv(i, 0.0) @@ -234,6 +235,7 @@ adc.average(16, True) adc.convst_spi(1) # dac.vina --> adc.ch4 +# J604 -- J210 adc.mux(4) #ch4 setup @@ -248,17 +250,19 @@ if 0: n = [] r = [] - for i in range(2**10): - x = 2**6 * i + nbits = 16 + for i in range(2**nbits): + x = 2**(16-nbits) * i dac.set(0, x) adc.read() #sham to trigger conversion - sleep(200e-6) #ensure 160us conversion time delay + sleep(160e-6) #ensure 160us conversion time delay n.append(x) v = adc.read() r.append(v) - print x, v + if i % 256 == 0: + print x, v - if 0: + if 1: figure() plot(n, r) xlabel('DAC code') diff --git a/python-lib/usbio.py b/python-lib/usbio.py index 1424c5a..f39af29 100644 --- a/python-lib/usbio.py +++ b/python-lib/usbio.py @@ -760,7 +760,8 @@ class AD524x(object): class DAC8568(object): CTL_WIDTH = 32 DAC_WIDTH = 16 - POR_VALUE = 2**(DAC_WIDTH - 1) + #POR_VALUE = 2**(DAC_WIDTH - 1) + POR_VALUE = 0 ALL_CHANNELS = 0xf @@ -1343,15 +1344,16 @@ class DigiReg(AD524x): class DAC_atoi(DAC8568): """Specific configuration and calibration for devboard DAC.""" VREF = 2.5 - GAIN = 2.0 #part options C/D - #POR_VALUE = 0 #part C - POR_VALUE = DAC8568.DAC_WIDTH / 2 #part D + GAIN = 1.0 #part options A/B + #GAIN = 2.0 #part options C/D + POR_VALUE = 0 #part A/C + #POR_VALUE = DAC8568.DAC_WIDTH / 2 #part B/D #zero-code output voltages VOS = ( 0.0, 0.0, 0.0, - 5e-3, + 0.0, 0.0, 0.0, 0.0, -- 2.25.1